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ZL50050
8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs Data Sheet Features
* 8,192-channel x 8,192-channel non-blocking unidirectional switching.The Backplane and Local inputs and outputs can be combined to form a non-blocking switching matrix with 32 input streams and 32 output streams 4,096-channel x 4,096-channel non-blocking Backplane input to Local output stream switch 4,096-channel x 4,096-channel non-blocking Local input to Backplane output stream switch 4,096-channel x 4,096-channel non-blocking Backplane input to Backplane output switch 4,096-channel x 4,096-channel non-blocking Local input to Local output stream switch Rate conversion on all data paths, Backplane-toLocal, Local-to-Backplane, Backplane-toBackplane and Local-to-Local streams Backplane port accepts 16 input and 16 output ST-BUS streams with data rates of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any combination, or a fixed allocation of 8 input and 8 output streams at 32.768 Mbps Local port accepts 16 input and 16 output STBUS streams with data rates of 2.048 Mbps, * * * * * * Ordering Information ZL50050GAC 196 Ball PBGA Trays ZL50050GAG2 196 Ball PBGA** Trays *Pb Free Tin/Silver/Copper -40C to +85C 4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any combination, or a fixed allocation of 8 input and 8 output streams at 32.768 Mbps Exceptional input clock jitter tolerance (17ns for 16Mbps or lower data rates, 14ns for 32 Mbps) Per-stream channel and bit delay for Local and Backplane input streams Per-stream advancement for Local and Backplane output streams Constant 2-frame throughput delay for frame integrity Per-channel high impedance output control for Local and Backplane streams Per-channel driven-high output control for Local and Backplane streams
January 2006
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*
*
VDD_IO VDD_CORE
VSS (GND)
RESET
ODE
BSTi0-15
Backplane Data Memories (4,096 channels)
Local Interface
LSTi0-15
BSTo0-15 BCST0-1 BORS
Backplane Interface
Backplane Connection Memory (4,096 locations)
Local Connection Memory (4,096 locations)
Local Interface
LSTo0-15 LCST0-1
Local Data Memories (4,096 channels) Input Timing Unit
Output Timing Unit
LORS
FP8i
FP8o FP16o C8o C16o
C8i
PLL
Microprocessor Interface and Internal Registers
Test Port
VDD_PLL
DS CS R/W
A14-0
DTA
D15-0
TMS TDi TDo TCK TRST
Figure 1 - ZL50050 Functional Block Diagram 1
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ZL50050
* * * * * * * * * * * * High impedance-control outputs for external drivers on Local and Backplane ports Per-channel message mode for Local and Backplane output streams Connection memory block programming for fast device initialization BER testing for Local and Backplane ports. Automatic selection between ST-BUS and GCI-Bus operation Non-multiplexed Motorola microprocessor interface Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard Memory Built-In-Self-Test (BIST), controlled via microprocessor register 1.8 V core supply voltage 3.3 V I/O supply voltage 5 V tolerant inputs, outputs and I/Os Pin-to-pin compatible with Zarlink's MT90871 device
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Data Sheet
Note 1: For software compatibility between ZL50050 and MT90871, please refer to Section 2.6.
Applications
* * * * * * Central Office Switches (Class 5) Media Gateways Class-independent switches Access Concentrators Scalable TDM-Based Architectures Digital Loop Carriers
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Zarlink Semiconductor Inc.
ZL50050
Device Overview
Data Sheet
The ZL50050 has two data ports, the Backplane and the Local port. Both the Backplane and Local ports have two independent modes of operation, either 16 input and 16 output streams operated at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps, in any combination, or 8 input and 8 output streams operated at 32.768 Mbps. The ZL50050 contains two data memory blocks (Backplane and Local) to provide the following switching path configurations: * * * * * Input-to-Output Unidirectional, supporting 8 K x 8 K switching Backplane-to-Local Bi-directional, supporting 4 K x 4 K data switching, Local-to-Backplane Bi-directional, supporting 4 K x 4 K data switching, Backplane-to-Backplane Bi-directional, supporting 4 K x 4 K data switching. Local-to-Local Bi-directional, supporting 4 K x 4 K data switching.
The device contains two connection memory blocks, one for the Backplane output and one for the Local output. Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly from the connection memory contents (Message Mode). In Connection Mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (stored in data memory) to be switched. In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output streams on a per channel basis. This feature is useful for transferring control and status information to external circuits or other ST-BUS devices. The device uses a master frame pulse (FP8i) and master clock (C8i) to define the input frame boundary and timing for both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a GCIBus style frame pulse is being used. There is a two-frame delay from the time RESET is de-asserted to the establishment of full switch functionality. During this period, the input frame pulse format is determined before switching begins. The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the outputs of the Backplane and Local ports. A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and switching configurations. The microprocessor port provides access for Register read/write, Connection Memory read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and 4 control signals. The microprocessor may monitor channel data in the Backplane and Local data memories. The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port. The ZL50050 is available in one package: * a 15 mm x 15 mm body, 1mm ball-pitch, 196-PBGA.
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Zarlink Semiconductor Inc.
ZL50050 Table of Contents
Data Sheet
1.0 Unidirectional and Bi-directional Switching Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.1 Flexible Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1.1 Non-Blocking Unidirectional Configuration (Typical System Configuration) . . . . . . . . . . . . . . . . . . 19 1.1.2 Non-Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1.3 Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 Switching Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1.1 Unidirectional Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1.2 Backplane-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1.3 Local-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1.4 Backplane-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1.5 Local-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1.6 Port Data Rate Modes and Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1.7 Local Port Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.1.7.1 Local Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.1.7.2 Local Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1.8 Backplane Port Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1.8.1 Backplane Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1.8.2 Backplane Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2 Frame Pulse Input and Master Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3 Input Frame Pulse and Generated Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4 Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator. . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.5 Input Clock Jitter Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.6 Backward Compatibility with MT90871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.0 Input and Output Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1 Input Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.1 Input Channel Delay Programming (Backplane and Local Input Streams) . . . . . . . . . . . . . . . . . . . 27 3.1.2 Input Bit Delay Programming (Backplane and Local Input Streams) . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2 Output Advancement Programming (Backplane and Local Output Streams) . . . . . . . . . . . . . . . . . . . . . . 29 4.0 Port High-Impedance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1 LORS/BORS Asserted LOW, Non-32Mbps Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2 LORS/BORS Asserted LOW, 32 Mbps Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.3 LORS/BORS Asserted HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.0 Bit Error Rate Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.0 Device Power-up, Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.0 Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1 Local Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.2 Backplane Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3.1 Memory Block Programming Procedure: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.0 Memory Built-In-Self-Test (BIST) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.2 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.1 Test Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.2 Test Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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Zarlink Semiconductor Inc.
ZL50050 Table of Contents
Data Sheet
11.2.2.3 The Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.3 Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.0 Memory Address Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1 Local Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.2 Backplane Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.3 Local Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.4 Backplane Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.0 Internal Register Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.0 Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14.1 Control Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14.2 Block Programming Register (BPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 14.3 Bit Error Rate Test Control Register (BERCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 14.4 Local Input Channel Delay Registers (LCDR0 to LCDR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 14.4.1 Local Channel Delay Bits 8-0 (LCD8 - LCD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 14.5 Local Input Bit Delay Registers (LIDR0 to LIDR15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14.5.1 Local Input Delay Bits 4-0 (LID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14.6 Backplane Input Channel Delay Registers (BCDR0 to BCDR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14.6.1 Backplane Channel Delay Bits 8-0 (BCD8 - BCD0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14.7 Backplane Input Bit Delay Registers (BIDR0 to BIDR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 14.7.1 Backplane Input Delay Bits 4-0 (BID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 14.8 Local Output Advancement Registers (LOAR0 to LOAR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 14.8.1 Local Output Advancement Bits 1-0 (LOA1-LOA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 14.9 Backplane Output Advancement Registers (BOAR0 - BOAR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 14.9.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 14.10 Local Bit Error Rate (BER) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.10.1 Local BER Start Send Register (LBSSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.10.2 Local Transmit BER Length Register (LTXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.10.3 Local Receive BER Length Register (LRXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.10.4 Local BER Start Receive Register (LBSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14.10.5 Local BER Count Register (LBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14.11 Backplane Bit Error Rate (BER) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.11.1 Backplane BER Start Send Register (BBSSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.11.2 Backplane Transmit BER Length Register (BTXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.11.3 Backplane Receive BER Length Register (BRXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.11.4 Backplane BER Start Receive Register (BBSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.11.5 Backplane BER Count Register (BBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14.12 Local Bit Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14.12.1 Local Input Bit Rate Registers (LIBRR0 - LIBRR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14.12.2 Local Output Bit Rate Registers (LOBRR0 - LOBRR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 14.13 Backplane Bit Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 14.13.1 Backplane Input Bit Rate Registers (BIBRR0 - BIBRR15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 14.13.2 Backplane Output Bit Rate Registers (BOBRR0 - BOBRR15) . . . . . . . . . . . . . . . . . . . . . . . . . . 75 14.14 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 14.15 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 15.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 16.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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Zarlink Semiconductor Inc.
ZL50050 List of Figures
Data Sheet
Figure 1 - ZL50050 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50050 PBGA Connections (196 PBGA, 15 mm x 15 mm) Pin Diagram (as viewed through top of package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3 - 8,192 x 8,192 Channels (16 Mbps), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 4 - 4,096 x 4,096 Channels (16 Mbps), Bi-directional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 5 - 6,144 by 2,048 Channels Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 6 - ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 7 - Input and Output (Generated) Frame Pulse Alignment for Different Data Rates . . . . . . . . . . . . . . . . . 25 Figure 8 - Backplane and Local Input Channel Delay Timing Diagram (assuming 8 Mbps operation) . . . . . . . . . 27 Figure 9 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mbps . . . . . . . . . . . . . . . . . 28 Figure 10 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for Data Rate of 8 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 11 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 16 Mbps . . . . . . . . . . . 30 Figure 12 - Local/Backplane Port External High-Impedance Control Bit Timing (Non-32 Mbps Mode). . . . . . . . . 34 Figure 13 - Local and Backplane Port External High-Impedance Control Timing (32 Mbps Mode). . . . . . . . . . . . 38 Figure 14 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch0 Switched to Output Ch0 . . . . 40 Figure 15 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch0 Switched to Output Ch13 . . . 40 Figure 16 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch13 Switched to Output Ch0 . . . 40 Figure 17 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch0 Switched to Output Ch0 . . . . 41 Figure 18 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch0 Switched to Output Ch13 . . . 41 Figure 19 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch13 Switched to Output Ch0 . . . 41 Figure 20 - Examples of BER Transmission Channels on a 16 Mbps Output Stream . . . . . . . . . . . . . . . . . . . . . . 42 Figure 21 - Hardware RESET De-assertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 22 - Frame Boundary Conditions, ST-BUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 23 - Frame Boundary Conditions, GCI-Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 24 - Input and Output Clock Timing Diagram for ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 25 - Input and Output Clock Timing Diagram for GCI-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 26 - ST-BUS Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps) . . . . . . . . . . . . . . . . . . . . 85 Figure 27 - ST-BUS Local/Backplane Data Timing Diagram (32 Mbps, 16 Mbps). . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 28 - GCI-Bus Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps) . . . . . . . . . . . . . . . . . . . 87 Figure 29 - GCI-Bus Local/Backplane Data Timing Diagram (32 Mbps, 16 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 30 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 31 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 32 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 33 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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Zarlink Semiconductor Inc.
ZL50050 List of Tables
Data Sheet
Table 1 - Per-stream Input and Output Data Rate Selection: Backplane and Local, Non-32 Mbps Mode and 32 Mbps Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 2 - Local and Backplane Output Enable Control Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 3 - L/BCSTo Allocation of Channel Control Bits to Output Streams (Non-32 Mbps Mode). . . . . . . . . . . . . . 32 Table 4 - L/BCSTo Allocation of Channel Control Bits to Output Streams (32 Mbps Mode) . . . . . . . . . . . . . . . . . 36 Table 5 - Variable Range for Input Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 6 - Variable Range for Output Streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 7 - Data Throughput Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 8 - Local and Backplane Connection Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 9 - Local Connection Memory in Block Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 10 - Backplane Connection Memory in Block Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 11 - Address Map for Data and Connection Memory Locations (A14 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 12 - Local Data Memory (LDM) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 13 - Backplane Data Memory (BDM) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 14 - LCM Bits for Non-32Mbps Source-to-Local Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 15 - LCM Bits for 32 Mbps Source-to-Local Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 16 - BCM Bits for Non-32Mbps Source-to-Backplane Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 17 - BCM Bits for 32 Mbps Source-to-Backplane Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 18 - Address Map for Registers (A14 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 19 - Control Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 20 - Block Programming Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 21 - Bit Error Rate Test Control Register (BERCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 22 - Local Input Channel Delay Register (LCDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 23 - Local Input Channel Delay (LCD) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 24 - Local Input Bit Delay Register (LIDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 25 - Local Input Bit Delay and Sampling Point Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 26 - Backplane Input Channel Delay Register (BCDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 27 - Backplane Input Channel Delay (BCD) Programming Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 28 - Backplane Input Bit Delay Register (BIDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 29 - Backplane Input Bit Delay and Sampling Point Programming Table. . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 30 - Local Output Advancement Register (LOAR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 31 - Local Output Advancement (LOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 32 - Backplane Output Advancement Register (BOAR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 33 - Backplane Output Advancement (BOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 34 - Local BER Start Send Register (LBSSR) Bits in Non-32 Mbps Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 35 - Local BER Start Send Register (LBSSR) Bits in 32 Mbps Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 36 - Local BER Length Register (LTXBLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 37 - Local Receive BER Length Register (LRXBLR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 38 - Local BER Start Receive Register (LBSRR) Bits for Non-32 Mbps Mode . . . . . . . . . . . . . . . . . . . . . . 70 Table 39 - Local BER Start Receive Register (LBSRR) Bits for 32 Mbps Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 40 - Local BER Count Register (LBCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 41 - Backplane BER Start Send Register (BBSSR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 42 - Backplane Transmit BER Length (BTXBLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 43 - Backplane Receive BER Length (BRXBLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 44 - Backplane BER Start Receive Register (BBSRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 45 - Backplane BER Count Register (BBCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 46 - Local Input Bit Rate Register (LIBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 47 - Local Input Bit Rate (LIBR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 48 - Local Output Bit Rate Register (LOBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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Zarlink Semiconductor Inc.
ZL50050 List of Tables
Data Sheet
Table 49 - Local Output Bit Rate (LOBR) Programming Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 50 - Backplane Input Bit Rate Register (BIBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 52 - Backplane Output Bit Rate Register (BOBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 53 - Backplane Output Bit Rate (BOBRR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 54 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 55 - Device Identification Register (DIR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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Zarlink Semiconductor Inc.
ZL50050
Pinout Diagram: (as viewed through top of package) A1 corner identified by metallized marking, mold indent, ink dot, or right-angled corner.
Data Sheet
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
BSTo1
BSTo2
A4
A5
A8
A9
A12
A13
R/W
CS
TMS
TDo
BCSTo0
TRST
B
A0
BSTo5
BSTo0
A1
A2
A7
A11
A14
ODE
TDi
TCK
LCSTo1
LSTo0
LSTo1
C
IC_GND BSTo7
BSTo8
BSTo3
BSTo4
A6
A10
DS
RESET BCSTo1 IC_GND LCSTo0 IC_GND
LSTo3
D
IC_GND BSTo6
BSTo10
GND
A3
VDD_IO VDD_IO VDD_IO
DTA
VDD_IO
GND
LSTo4
LSTo6
LSTo2
E
BSTo12 BSTo11 BSTo13 VDD_IO
GND
VDD_ CORE GND
VDD_ CORE GND
VDD_ CORE GND
VDD_ CORE GND
GND
VDD_IO
LSTo8
LSTo7
LSTo5
F
BSTo9
BSTo14 BSTo15 VDD_IO
VDD_ CORE VDD_ CORE VDD_ CORE VDD_ CORE GND
VDD_ CORE VDD_ CORE VDD_ CORE VDD_ CORE GND
VDD_IO LSTo12 LSTo13
LSTo9
G
BSTi0
BORS
VDD_ CORE BSTi3
VDD_IO
GND
GND
GND
GND
VDD_IO LSTo11 LSTo15 LSTo10
H
BSTi1
BSTi2
VDD_IO
GND
GND
GND
GND
VDD_IO
VDD_ CORE LSTi5
LORS
LSTo14
J
BSTi4
BSTi5
BSTi7
VDD_IO
GND
GND
GND
GND
VDD_IO
LSTi1
LSTi2
K
BSTi6
BSTi9
BSTi13 VDD_IO
VDD_ CORE
VDD_ CORE
VDD_ CORE
VDD_ CORE
VDD_IO LSTi15
LSTi3
LSTi0
L
BSTi8
BSTi11
BSTi14
GND
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
GND
LSTi14
LSTi8
LSTi6
M
BSTi10
BSTi15
D15
D14
D12
D5
IC_GND IC_GND
C16o
FP8i
LSTi13
LSTi10
LSTi7
LSTi4
N
BSTi12
D13
D10
D11
D7
D3
D0
IC_GND
VDD_ PLL IC_ OPEN
C8o
FP8o
LSTi11
LSTi12
LSTi9
P
GND
D9
D8
D6
D4
D2
D1
IC_GND
C8i
IC_ OPEN
FP16o
GND
GND
Figure 2 - ZL50050 PBGA Connections (196 PBGA, 15 mm x 15 mm) Pin Diagram
(as viewed through top of package)
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Zarlink Semiconductor Inc.
ZL50050
Pin Description ZL50050 Package Coordinates (196-ball PBGA)
Data Sheet
Pin Name
Description
Device Timing C8i P10 Master Clock (5 V Tolerant Schmitt-Triggered Input). This pin accepts an 8.192 MHz clock. The internal frame boundary is aligned with the clock falling or rising edge, as controlled by the C8IPOL bit in the Control Register. Input data on both the Backplane and Local sides (BSTi0-15 and LSTi0-15) must be aligned to this clock and the accompanying input frame pulse, FP8i. Frame Pulse Input (5 V Tolerant Schmitt-Triggered Input). When the Frame Pulse Width bit (FPW) of the Control Register is LOW (default), this pin accepts a 122 ns-wide frame pulse. When the FPW bit is HIGH, this pin accepts a 244 ns-wide frame pulse. The device will automatically detect whether an ST-BUS or GCI-Bus style frame pulse is applied. Input data on both the Backplane and Local sides (BSTi0-15 and LSTi0-15) must be aligned to this frame pulse and the accompanying input clock, C8i. C8o Output Clock (5 V Tolerant Three-state Output). This pin outputs an 8.192 MHz clock generated within the device. The clock falling edge or rising edge is aligned with the output frame boundary presented on FP8o; this edge polarity alignment is controlled by the COPOL bit of the Control Register. Output data on both the Backplane and Local sides (BSTo0-15 and LSTo0-15) will be aligned to this clock and the accompanying output frame pulse, FP8o. Frame Pulse Output (5 V Tolerant Three-state Output). When the Frame Pulse Width bit (FPW) of the Control Register is LOW (default), this pin outputs a 122ns-wide frame pulse. When the FPW bit is HIGH, this pin outputs a 244 ns-wide frame pulse. The frame pulse, running at 8 kHz rate, will have the same format (ST-BUS or GCI-Bus) as the input frame pulse (FP8i). Output data on both the Backplane and Local sides (BSTo0-15 and LSTo0-15) will be aligned to this frame pulse and the accompanying output clock, C8o. C16o Output Clock (5 V Tolerant Three-state Output). This pin outputs a 16.384 MHz clock generated within the device. The clock falling edge or rising edge is aligned with the output frame boundary presented on FP16o; this edge polarity alignment is controlled by the COPOL bit of the Control Register. Output data on both the Backplane and Local sides (BSTo0-15 and LSTo0-15) will be aligned to this clock and the accompanying output frame pulse, FP16o. Frame Pulse Output (5 V Tolerant Three-state Output). When the Frame Pulse Width bit (FPW) of the Control Register is LOW (default), this pin outputs a 61 ns-wide frame pulse. When the FPW bit is HIGH, this pin outputs a 122 ns-wide frame pulse. The frame pulse, running at 8 kHz rate, will have the same format (ST-BUS or GCI-Bus) as the input frame pulse (FP8i). Output data on both the Backplane and Local sides (BSTo0-15 and LSTo0-15) will be aligned to this frame pulse and the accompanying output clock, C16o.
FP8i
M10
C8o
N10
FP8o
N11
C16o
M9
FP16o
P12
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Zarlink Semiconductor Inc.
ZL50050
Pin Description (continued) ZL50050 Package Coordinates (196-ball PBGA)
Data Sheet
Pin Name
Description
Backplane and Local Inputs BSTi0-7 G1, H1, H2, H3, J1, J2, K1, J3 Backplane Serial Input Streams 0 to 7 (5 V Tolerant Inputs with Internal Pull-downs). In Backplane Non-32 Mbps Mode, these pins accept serial TDM data streams at a data rate of: 16.384 Mbps (with 256 channels per stream), 8.192 Mbps (with 128 channels per stream), 4.096 Mbps (with 64 channels per stream) or 2.048 Mbps (with 32 channels per stream). The data rate is independently programmable for each input stream. In Backplane 32 Mbps Mode, these pins accept serial TDM data streams at a fixed data rate of 32.768 Mbps (with 512 channels per stream). BSTi8-15 L1, K2, M1, L2, N1, K3, L3, M2 Backplane Serial Input Streams 8 to 15 (5 V Tolerant Inputs with Internal Pull-downs). In Backplane Non-32 Mbps Mode, these pins accept serial TDM data streams at a data rate of: 16.384 Mbps (with 256 channels per stream), 8.192 Mbps (with 128 channels per stream), 4.096 Mbps (with 64 channels per stream) or 2.048 Mbps (with 32 channels per stream). The data rate is independently programmable for each input stream. In Backplane 32 Mbps Mode, these pins are unused and should be externally connected to a defined logic level. LSTi0-7 K14, J13, J14, K13, M14, J12, L14, M13 Local Serial Input Streams 0 to 7 (5 V Tolerant Inputs with Internal Pull-downs). In Local Non-32 Mbps Mode, these pins accept serial TDM data streams at a data rate of: 16.384 Mbps (with 256 channels per stream), 8.192 Mbps (with 128 channels per stream), 4.096 Mbps (with 64 channels per stream) or 2.048 Mbps (with 32 channels per stream). The data rate is independently programmable for each input stream. In Local 32 Mbps Mode, these pins accept serial TDM data streams at a fixed data rate of 32.768 Mbps (with 512 channels per stream).
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Zarlink Semiconductor Inc.
ZL50050
Pin Description (continued) ZL50050 Package Coordinates (196-ball PBGA) L13, N14, M12, N12, N13, M11, L12, K12
Data Sheet
Pin Name
Description
LSTi8-15
Local Serial Input Streams 8 to 15 (5 V Tolerant Inputs with Internal Pull-downs). In Local Non-32 Mbps Mode, these pins accept serial TDM data streams at a data rate of: 16.384 Mbps (with 256 channels per stream), 8.192 Mbps (with 128 channels per stream), 4.096 Mbps (with 64 channels per stream) or 2.048 Mbps (with 32 channels per stream). The data rate is independently programmable for each input stream. In Local 32 Mbps Mode, these pins are unused and should be externally connected to a defined logic level.
Backplane and Local Outputs and Control ODE B9 Output Drive Enable (5 V Tolerant Input with Internal Pull-up). An asynchronous input providing Output Enable control to the BSTo0-15, LSTo0-15, BCSTo0-1, and LCSTo0-1 outputs. When LOW, the BSTo0-15 and LSTo0-15 outputs are driven HIGH or high impedance (dependent on the BORS and LORS pin settings respectively) and the outputs BCSTo0-1 and LCSTo0-1 are driven low. When HIGH, the outputs BSTo0-15, LSTo0-15, BCSTo0-1, and LCSTo0-1 are enabled. BORS G2 Backplane Output Reset State (5 V Tolerant Input with Internal Pull-down). When this input is LOW, the device will initialize with the BSTo0-15 outputs driven high, and the BCSTo0-1 outputs driven low. Following initialization, the Backplane stream outputs are always active and a high impedance state, if required on a per-channel basis, may be implemented with external buffers controlled by outputs BCSTo0-1. When this input is HIGH, the device will initialize with the BSTo0-15 outputs at high impedance and the BCSTo0-1 outputs driven low. Following initialization, the Backplane stream outputs may be set active or high impedance using the ODE pin or on a per-channel basis with the BE bit in the Backplane Connection Memory.
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Zarlink Semiconductor Inc.
ZL50050
Pin Description (continued) ZL50050 Package Coordinates (196-ball PBGA) B3, A1, A2, C4, C5, B2, D2, C2
Data Sheet
Pin Name
Description
BSTo0-7
Backplane Serial Output Streams 0 to 7 (5 V Tolerant, Three-state Outputs with Slew-Rate Control). In Backplane Non-32 Mbps Mode, these pins output serial TDM data streams at a data rate of: 16.384 Mbps (with 256 channels per stream), 8.192 Mbps (with 128 channels per stream), 4.096 Mbps (with 64 channels per stream) or 2.048 Mbps (with 32 channels per stream). The data rate is independently programmable for each output stream. In Backplane 32 Mbps Mode, these pins output serial TDM data streams at a fixed data rate of 32.768 Mbps (with 512 channels per stream). Refer to the descriptions of the BORS and ODE pins for control of the output HIGH or high impedance state.
BSTo8-15
C3, F1, D3, E2, E1, E3, F2, F3
Backplane Serial Output Streams 8 to 15 (5 V Tolerant, Three-state Outputs with Slew-Rate Control). In Backplane Non-32 Mbps Mode, these pins output serial TDM data streams at a data rate of: 16.384 Mbps (with 256 channels per stream), 8.192 Mbps (with 128 channels per stream), 4.096 Mbps (with 64 channels per stream) or 2.048 Mbps (with 32 channels per stream). The data rate is independently programmable for each output stream. These pins are unused when the Backplane 32 Mbps Mode is selected. Therefore, the value output on these pins during Backplane 32 Mbps Mode (either driven-HIGH or high impedance) is dependent on the configuration of the BORS pin. Refer to the descriptions of the BORS and ODE pins for control of the output HIGH or high impedance state.
BCSTo0-1
A13, C10
Backplane Output Channel High-Impedance Control (5 V Tolerant, Three-state Outputs). These pins control external buffering individually for a set of Backplane output streams on a per-channel basis. When LOW, the external output buffer will be tri-stated. When HIGH, the external output buffer will be enabled. In Backplane Non-32 Mbps Mode (stream rates 2 Mbps to 16 Mbps): BCSTo0 is the output enable for BSTo0,2,4,6,8,10,12,14 BCSTo1 is the output enable for BSTo1,3,5,7,9,11,13,15 In Backplane 32 Mbps Mode (stream rate 32 Mbps): BCSTo0 is the output enable for BSTo0,2,4,6 BCSTo1 is the output enable for BSTo1,3,5,7 Refer to the descriptions of the BORS and ODE pins for control of the output LOW or active state.
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Zarlink Semiconductor Inc.
ZL50050
Pin Description (continued) ZL50050 Package Coordinates (196-ball PBGA) H13
Data Sheet
Pin Name
Description
LORS
Local Output Reset State (5 V Tolerant Input with Internal Pull-down). When this input is LOW, the device will initialize with the LSTo0-15 outputs driven high, and the LCSTo0-1 outputs driven low. Following initialization, the Local stream outputs are always active and a high impedance state, if required on a per-channel basis, may be implemented with external buffers controlled by outputs LCSTo0-1. When this input is HIGH, the device will initialize with the LSTo0-15 outputs at high impedance and the LCSTo0-1 outputs driven low. Following initialization, the Local stream outputs may be set active or high impedance using the ODE pin or on a per-channel basis with the LE bit in the Local Connection Memory.
LSTo0-7
B13, B14, D14, C14, D12, E14, D13, E13
Local Serial Output Streams 0 to 7 (5 V Tolerant Three-state Outputs with Slew-Rate Control). In Local Non-32 Mbps Mode, these pins output serial TDM data streams at a data rate of: 16.384 Mbps (with 256 channels per stream), 8.192 Mbps (with 128 channels per stream), 4.096 Mbps (with 64 channels per stream) or 2.048 Mbps (with 32 channels per stream). The data rate is independently programmable for each output stream. In Local 32 Mbps Mode, these pins output serial TDM data streams at a fixed data rate of 32.768 Mbps (with 512 channels per stream). Refer to the descriptions of the LORS and ODE pins for control of the output HIGH or high impedance state.
LSTo8-15
E12, F14, G14, G12, F12, F13, H14, G13
Local Serial Output Streams 8 to 15 (5 V Tolerant Three-state Outputs with Slew-Rate Control). In Local Non-32 Mbps Mode, these pins output serial TDM data streams at a data rate of: 16.384 Mbps (with 256 channels per stream), 8.192 Mbps (with 128 channels per stream), 4.096 Mbps (with 64 channels per stream) or 2.048 Mbps (with 32 channels per stream). The data rate is independently programmable for each output stream. These pins are unused when the Local 32 Mbps Mode is selected. Therefore, the value output on these pins during Local 32 Mbps Mode (either driven-HIGH or high impedance) is dependent on the configuration of the LORS pin. Refer to the descriptions of the LORS and ODE pins for control of the output HIGH or high impedance state.
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Zarlink Semiconductor Inc.
ZL50050
Pin Description (continued) ZL50050 Package Coordinates (196-ball PBGA) C12, B12
Data Sheet
Pin Name
Description
LCSTo0-1
Local Output Channel High-Impedance Control (5 V Tolerant Three-state Outputs). These pins control external buffering individually for a set of Local output streams on a per-channel basis. When LOW, the external output buffer will be tri-stated. When HIGH, the external output buffer will be enabled. In Local Non-32 Mbps Mode (stream rate 2 Mbps to 16 Mbps): LCSTo0 is the output enable for LSTo0,2,4,6,8,10,12,14 LCSTo1 is the output enable for LSTo1,3,5,7,9,11,13,15 In Local 32 Mbps Mode (stream rate 32 Mbps): LCSTo0 is the output enable for LSTo0,2,4,8 LCSTo1 is the output enable for LSTo1,3,5,7 Refer to descriptions of the LORS and ODE pins for control of the output LOW or active state.
Microprocessor Port Signals A0 - A14 B1, B4, B5, D5, A3, A4, C6, B6, A5, A6, C7, B7, A7, A8, B8 N7, P7, P6, N6, P5, M6, P4, N5, P3, P2, N3, N4, M5, N2, M4, M3 A10 Address 0 - 14 (5 V Tolerant Inputs). These pins form the 15-bit address bus to the internal memories and registers. A0 = LSB Data Bus 0 - 15 (5 V Tolerant Inputs/Outputs with Slew-Rate Control). These pins form the 16-bit data bus of the microprocessor port. D0 = LSB Chip Select (5 V Tolerant Input). Active LOW input used by the microprocessor to enable the microprocessor port access. Note that a minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion of CS and/or DS to initiate the next access. Data Strobe (5 V Tolerant Input). This active LOW input works in conjunction with CS to enable the microprocessor port read and write operations. Note that a minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion of CS and/or DS to initiate the next access. Read/Write (5 V Tolerant Input). This input controls the direction of the data bus lines (D0-D15) during a microprocessor access. Data Transfer Acknowledgment (5 V Tolerant Three-state Output). This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required to hold a HIGH level. Note that a minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion of CS and/or DS to initiate the next access.
D0 - D15
CS
DS
C8
R/W DTA
A9 D9
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Zarlink Semiconductor Inc.
ZL50050
Pin Description (continued) ZL50050 Package Coordinates (196-ball PBGA) C9
Data Sheet
Pin Name
Description
RESET
Device Reset (5 V Tolerant Input with Internal Pull-up). This input (active LOW) asynchronously applies reset and synchronously releases reset to the device. In the reset state, the outputs LSTo0-15 and BSTo0-15 are set to a HIGH or high impedance state, depending on the state of the LORS and BORS external control pins, respectively. The assertion of RESET causes the LCSTo0-1 and BCSTo0-1 pins to be driven LOW (refer to Table 2). The assertion of this pin also clears the device registers and internal counters. Refer to Section 8.3 on page 44 for the timing requirements regarding this reset signal.
JTAG Control Signals TCK TMS TDi TDo B11 A11 B10 A12 Test Clock (5 V Tolerant Input). Provides the clock to the JTAG test logic. Test Mode Select (5 V Tolerant Input with Internal Pull-up). JTAG signal that controls the state transitions of the TAP controller. Test Serial Data In (5 V Tolerant Input with Internal Pull-up). JTAG serial test instructions and data are shifted in on this pin. Test Serial Data Out (5 V Tolerant Three-state Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in a high impedance state when JTAG is not enabled. Test Reset (5 V Tolerant Input with Internal Pull-up). Asynchronously initializes the JTAG TAP controller to the Test-Logic-Reset state. This pin must be pulsed LOW during power-up for JTAG testing. This pin must be held LOW for normal functional operation of the device.
TRST
A14
Power and Ground Pins VDD_IO D6, D7, D8, D10, E4, E11, F4, F11, G4, G11, H4, H11, J4, J11, K4, K11, L5, L6, L7, L8, L9, L10 E6, E7, E8, E9, F5, F10, G3, G5, G10, H5, H10, H12, J5, J10, K6, K7, K8, K9 N9 Power Supply for Periphery Circuits: +3.3 V
VDD_CORE
Power Supply for Core Circuits: +1.8 V
VDD_PLL
Power Supply for Analog PLL: +1.8 V
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Zarlink Semiconductor Inc.
ZL50050
Pin Description (continued) ZL50050 Package Coordinates (196-ball PBGA) D4, D11, E5, E10, F6, F7, F8, F9, G6, G7, G8, G9, H6, H7, H8, H9, J6, J7, J8, J9, K5, K10, L4, L11, P1, P13, P14 Ground.
Data Sheet
Pin Name
Description
VSS (GND)
Unused Pins IC_OPEN IC_GND P9, P11 C1, C11, C13, D1, M7, M8, N8, P8 Internal Connections - OPEN. These pins must be left unconnected. Internal Connections - GND. These pins must be tied LOW.
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Zarlink Semiconductor Inc.
ZL50050
1.0 Unidirectional and Bi-directional Switching Applications
Data Sheet
The ZL50050 has a maximum capacity of 8,192 input channels and 8,192 output channels. This is calculated from the maximum number of streams and channels: 32 input streams (16 Backplane, 16 Local) at 16.384 Mbps and 32 output streams (16 Backplane, 16 Local) at 16.384 Mbps. A typical mode of operation is to separate the input and output streams to form a unidirectional switch, as shown in Figure 3 below.
BSTi0-15 16 streams INPUT LSTi0-15 16 streams ZL50050
BSTo0-15 16 streams OUTPUT LSTo0-15 16 streams
Figure 3 - 8,192 x 8,192 Channels (16 Mbps), Unidirectional Switching In this system, the Backplane and Local input streams are combined, and the Backplane and Local output streams are combined, so that the switch appears as a 32 input stream by 32 output stream switch. This gives the maximum 8,192 x 8,192 channel capacity. Often a system design needs to differentiate between a Backplane and a Local side, or it needs to put the switch in a bi-directional configuration. In this case, the ZL50050 can be used as shown in Figure 4 to give 4,096 x 4,096 channel bi-directional capacity.
BSTi0-15 16 streams BACKPLANE BSTo0-15 16 streams ZL50050
LSTo0-15 16 streams LOCAL LSTi0-15 16 streams
Figure 4 - 4,096 x 4,096 Channels (16 Mbps), Bi-directional Switching In this system setup, the chip has a capacity of 4,096 input channels and 4,096 output channels on the Backplane side, as well as 4,096 input channels and 4,096 output channels on the Local side. Note that some or all of the output channels on one side can come from the other side, e.g., Backplane input to Local output switching. Note that in either configuration, the Backplane port can be operated in the Backplane 32 Mbps Mode, providing 512 channels on each of the 8 available input and output streams (BSTi0-7 and BSTo0-7) operating at a data rate of 32.768 Mbps, in conjunction with the Local streams (LSTi0-15 and LSTo0-15) operating at 16.384 Mbps (Local Non-32 Mbps Mode) or in conjunction with the Local streams (LSTi0-7 and LSTo0-7) operating at 32.768 Mbps (Local 32 Mbps Mode). Similarly, the Local port can be operated in the Local 32 Mbps Mode, providing 512 channels on each of the 8 available input and output streams (LSTi0-7 and LSTo0-7) operating at a data rate of 32.768 Mbps, in conjunction with the Backplane streams (BSTi0-15 and BSTo0-15) operating at 16.384 Mbps (Backplane Non-32 Mbps Mode) or in conjunction with the Backplane streams (BSTi0-7 and BSTo0-7) operating at 32.768 Mbps (Backplane 32 Mbps Mode).
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Zarlink Semiconductor Inc.
ZL50050
Data Sheet
The modes in which one port operates in 32 Mbps Mode while the other port operates in Non-32 Mbps Mode allow data rate conversion between 32.768 Mbps and 16.384 Mbps without loss to the switching capacity.
1.1
Flexible Configuration
The ZL50050 can be configured as an 8 K by 8 K non-blocking unidirectional digital switch, a 4 K by 4 K non-blocking bi-directional digital switch, or as a blocking switch with various switching capacities.
1.1.1
Non-Blocking Unidirectional Configuration (Typical System Configuration)
Because the input and output drivers are synchronous, the user can combine input Backplane streams and input Local streams as well as output Backplane streams and output Local streams to increase the total number of input and output streams of the switch in a unidirectional configuration, as shown in Figure 3. * 8,192-channel x 8,192-channel non-blocking switching from input to output streams
1.1.2
Non-Blocking Bi-directional Configuration
Another typical application is to configure the ZL50050 as a non-blocking 4 K by 4 K bi-directional switch, as shown in Figure 4: * * * * 4,096-channel x 4,096-channel non-blocking switching from Backplane input to Local output streams 4,096-channel x 4,096-channel non-blocking switching from Local input to Backplane output streams 4,096-channel x 4,096-channel non-blocking switching from Backplane input to Backplane output streams 4,096-channel x 4,096-channel non-blocking switching from Local input to Local output streams
1.1.3
Blocking Bi-directional Configuration
The ZL50050 can be configured as a blocking bi-directional switch if it is an application requirement. For example, it can be configured as a 6 K by 2 K bi-directional blocking switch, as shown in Figure 5: * * * * 6,144-channel x 2,048-channel blocking switching from Backplane input to Local output streams 2,048-channel x 6,144-channel blocking switching from Local input to Backplane output streams 6,144-channel x 6,144-channel non-blocking switching from Backplane input to Backplane output streams 2,048-channel x 2,048-channel non-blocking switching from Local input to Local output streams
BSTi0-15 LSTi0-7 BSTo0-15 LSTo0-7 Total 24 streams input and 24 streams output 6 K by 6 K
ZL50050 6 K by 2 K 2 K by 2 K 2 K by 6 K LSTi8-15 LSTo8-15
Total 8 streams input and 8 streams output
Figure 5 - 6,144 by 2,048 Channels Blocking Bi-directional Configuration
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Zarlink Semiconductor Inc.
ZL50050
2.0
2.1
Data Sheet
Functional Description
Switching Configuration
The device supports five switching configurations: (1) Unidirectional switch, (2) Backplane-to-Local, (3) Local-to-Backplane, (4) Backplane-to-Backplane, and (5) Local-to-Local. The following sections describe the switching paths in detail. Configurations (2) - (5) enable a non-blocking bi-directional switch with 4,096 Backplane input/output channels at Backplane stream data rates of 16.384 Mbps or 32.768 Mbps, and 4,096 Local input/output channels at Local stream data rates of 16.384 Mbps or 32.768 Mbps. The switching paths of configurations (2) to (5) may be operated simultaneously. When the lower data-rates of 8.192, 4.096 and 2.048 Mbps are included, there will be a corresponding reduction in switch capacity although conversion between differing rates will be maintained.
2.1.1
Unidirectional Switch
The device can be configured as a 8,192 x 8,192 unidirectional switch by grouping together all input streams and all output streams. All streams can be operated at a data rate of 16.384 Mbps or 32.768 Mbps, or a combination of 16.384 Mbps and 32.768 Mbps (i.e., one rate on the Local streams and the other rate on the Backplane streams). Lower data rates may be used with a corresponding reduction in switch capacity.
2.1.2
Backplane-to-Local Path
The device can provide data switching between the Backplane input port and the Local output port. The Local Connection Memory determines the switching configurations.
2.1.3
Local-to-Backplane Path
The device can provide data switching between the Local input port and the Backplane output port. The Backplane Connection Memory determines the switching configurations.
2.1.4
Backplane-to-Backplane Path
The device can provide data switching between the Backplane input and output ports. The Backplane Connection Memory determines the switching configurations.
2.1.5
Local-to-Local Path
The device can provide data switching between the Local input and output ports. The Local Connection Memory determines the switching configurations.
2.1.6
Port Data Rate Modes and Selection
The bit rate for each input stream is selected by writing to dedicated input bit rate registers, BIBRR0 to BIBRR15 for Backplane Input Bit Rate Registers (see Table 50) and LIBRR0 to LIBRR15 for Local Input Bit Rate Registers (see Table 46). The bit rate for each output stream is selected by writing to dedicated output bit rate registers, BOBRR0 to BOBRR15 for Backplane Output Bit Rate Registers (see Table 52) and LOBRR0 to LOBRR15 for Local Output Bit Rate Registers (see Table 48). If the Backplane 32Mbps Mode is selected by setting the Control Register bit MODE32B HIGH, the settings in BIBRRn and BOBRRn are ignored. Similarly, if the Local 32Mbps Mode is selected by setting the Control Register bit MODE32L HIGH, the settings in LIBRRn and LOBRRn are ignored.
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Zarlink Semiconductor Inc.
ZL50050
Stream Numbers Local Input streams - LSTi0-7 Local Input streams - LSTi8-15 Backplane Input streams - BSTi0-7 Backplane Input streams - BSTi8-15 Local Output streams - LSTo0-7 Local Output streams - LSTo8-15 Backplane Output streams - BSTo0-7 Backplane Output streams - BSTo8-15
Data Sheet
Rate Selection Capability (for each individual stream) 2.048, 4.096, 8.192 or 16.384 Mbps in Local Non-32 Mbps Mode. All streams at 32.768 Mbps in Local 32 Mbps Mode. 2.048, 4.096, 8.192 or 16.384 Mbps in Local Non-32 Mbps Mode. Unused in Local 32 Mbps Mode. 2.048, 4.096, 8.192 or 16.384 Mbps in Backplane Non-32 Mbps Mode. All streams at 32.768 Mbps in Backplane 32Mbps Mode. 2.048, 4.096, 8.192 or 16.384Mbps in Backplane Non-32 Mbps Mode. Unused in Backplane 32 Mbps Mode. 2.048, 4.096, 8.192 or 16.384 Mbps in Local Non-32 Mbps Mode. All streams at 32.768 Mbps in Local 32 Mbps Mode. 2.048, 4.096, 8.192 or 16.384 Mbps in Local Non-32 Mbps Mode. Unused in Local 32 Mbps Mode. 2.048, 4.096, 8.192 or 16.384 Mbps in Backplane Non-32 Mbps Mode. All streams at 32.768 Mbps in Backplane 32 Mbps Mode. 2.048, 4.096, 8.192 or 16.384 Mbps in Backplane Non-32 Mbps Mode. Unused in Backplane 32 Mbps Mode.
Table 1 - Per-stream Input and Output Data Rate Selection: Backplane and Local, Non-32 Mbps Mode and 32 Mbps Mode
2.1.7
Local Port Rate Selection
The Local port has 16 input (LSTi0-15) and 16 output (LSTo0-15) data streams. The Local streams can be operated in one of two modes, Local Non-32 Mbps Mode and Local 32 Mbps Mode. The Local stream data rates are not affected by the operating mode of the Backplane port. The operating mode of the Local side is determined by the state of the Control Register bit MODE32L. Setting this bit HIGH will invoke the Local 32 Mbps Mode. Setting the bit LOW will invoke the Non-32 Mbps Mode. The default value of this bit on device reset is LOW. The timing of the input and output clocks and frame pulses is shown in Figure 7, Input and Output (Generated) Frame Pulse Alignment for Different Data Rates. Local Non-32 Mbps Mode: Each of the Local streams (LSTi0-15 and LSTo0-15) can be independently programmed for a data rate of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Local 32 Mbps Mode: 8 of the Local input streams (LSTi0-7) and 8 of the Local output streams (LSTo0-7) operate at a fixed rate of 32.768 Mbps. In this mode, the remaining input and output streams are unused.
2.1.7.1
Local Input Port
The input traffic on the Local streams are aligned based on the FP8i and C8i input timing signals. Each input stream, LSTi0-15, can be individually set to operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps by programming the LIBR1-0 bits in the Local Input Bit Rate Register (LIBRR0-15). The Local streams can also be set to operate at 32.768 Mbps. When the MODE32L bit in the Control Register is set high, the first 8 input streams, LSTi0-7, operate at 32.768 Mbps and the remaining 16 streams, LSTi8-15, will not be used and must be connected to a defined logic level.
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Zarlink Semiconductor Inc.
ZL50050
2.1.7.2 Local Output Port
Data Sheet
The output traffic on the Local streams are aligned based on the FP8o and C8o output timing signals. Operation of stream data in Connection Mode or Message Mode is determined by the state of the LMM bit of the Local Connection Memory. The channel high impedance state is controlled by the LE bit of the Local Connection Memory. The data source (i.e., from the Local or Backplane Data Memory) is determined by the LSRC bit of the Local Connection Memory. Refer to Section 9.1, Local Connection Memory, and Section 12.3, Local Connection Memory Bit Definition for more details. Each output stream, LSTo0-15, can be individually set to operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps by programming the LOBR1-0 bits in the Local Output Bit Rate Register (LOBRR0-15). The Local streams can also be set to operate at 32.768 Mbps. When the MODE32L bit in the Control Register is set high, the first 8 output streams, LSTo0-7, operate at 32.768 Mbps and the remaining 8 streams, LSTo8-15, will not be used and must be connected to a defined logic level.
2.1.8
Backplane Port Rate Selection
The Backplane port has 16 input (BSTi0-15) and 16output (BSTo0-15) data streams. The Backplane streams can be operated in one of two modes, Backplane Non-32 Mbps Mode and Backplane 32 Mbps Mode. The Backplane stream data rates are not affected by the operating mode of the Local port. The operating mode of the Backplane side is determined by the state of the Control Register bit MODE32B. Setting this bit HIGH will invoke the Backplane 32 Mbps Mode. Setting the bit LOW will invoke the Non-32 Mbps Mode. The default value of this bit on device reset is LOW. The timing of the input and output clocks and frame pulses is shown in Figure 7, Input and Output (Generated) Frame Pulse Alignment for Different Data Rates. Backplane Non-32 Mbps Mode: Each of the Backplane streams (BSTi0-15 and BSTo0-15) can be independently programmed for a data rate of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Backplane 32 Mbps Mode: 8 of the Backplane input streams (BSTi0-7) and 8 of the Backplane output streams (BSTo0-7) operate at a fixed rate of 32.768 Mbps. In this mode, the remaining input and output streams are unused.
2.1.8.1
Backplane Input Port
The input traffic on the Backplane streams are aligned based on the FP8i and C8i input timing signals. Each input stream, BSTi0-15, can be individually set to operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps by programming the BIBR1-0 bits in the Backplane Input Bit Rate Register (BIBRR0-15). The Backplane streams can also be set to operate at 32.768 Mbps. When the MODE32B bit in the Control Register is set high, the first 8 input streams, BSTi0-7, operate at 32.768 Mbps and the remaining 8 streams, BSTi8-15, will not be used and must be connected to a defined logic level.
2.1.8.2
Backplane Output Port
The output traffic on the Backplane streams are aligned based on the FP8o and C8o output timing signals. Operation of stream data in Connection Mode or Message Mode is determined by the state of the BMM bit of the Backplane Connection Memory and the channel high impedance state is controlled by the BE bit of the Backplane Connection Memory. The data source (i.e. from the Local or Backplane Data Memory) is determined by the BSRC bit of the Backplane Connection Memory. Refer to Section 9.2, Backplane Connection Memory and Section 12.4, Backplane Connection Memory Bit Definition for more details. Each output stream, BSTo0-15, can be individually set to operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps by programming the BOBR1-0 bits in the Backplane Output Bit Rate Register (BOBRR0-15). The Backplane streams can also be set to operate at 32.768 Mbps. When the MODE32B bit in the Control Register is set high, the first 8 output streams, BSTo0-7, operate at 32.768 Mbps and the remaining 8 streams, BSTo8-15, will not be used and must be connected to a defined logic level.
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Zarlink Semiconductor Inc.
ZL50050
2.2 Frame Pulse Input and Master Input Clock Timing
Data Sheet
The input frame pulse (FP8i) is an 8 kHz input signal active for 122 ns or 244 ns at the frame boundary. The FPW bit in the Control Register must be set according to the applied pulse width. See Pin Description and Table 19, "Control Register Bits" on page 53, for details. The active state and timing of FP8i can conform either to the ST-BUS or to the GCI-Bus as shown in Figure 6, ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates. The ZL50050 device will automatically detect whether an ST-BUS or a GCI-Bus style frame pulse is being used for the master frame pulse (FP8i). The output frame pulses (FP8o and FP16o) are always of the same style (ST-BUS or GCI-Bus) as the input frame pulse. The active edge of the input clock (C8i) shall be selected by the state of the Control Register bit C8IPOL. Note that the active edge of ST-BUS is falling edge, which is the default mode of the device, while GCI-Bus uses rising edge as the active edge. Although GCI frame pulse will be automatically detected, to fully conform to GCI-Bus operation, the device should be set to use C8i rising edge as the active edge (by setting bit C8IPOL HIGH) when GCI-Bus is used. For the purposes of describing the device operation, the remaining part of this document assumes the ST-BUS frame pulse format with a single width frame pulse of 122 ns and a falling active clock-edge, unless explicitly stated otherwise. In addition, the device provides FP8o, FP16o, C8o and C16o outputs to support external devices which connect to the output ports. The generated frame pulses (FP8o, FP16o) will be provided in the same format as the master frame pulse (FP8i). The polarity of C8o and C16o, at the frame boundary, can be controlled by the Control Register bit, COPOL. An analog phase lock loop (APLL) is used to multiply the input clock frequency on C8i to generate an internal clock signal operating at 131.072 MHz.
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Zarlink Semiconductor Inc.
ZL50050
FP8i (ST-BUS) (8 kHz) C8i (ST-BUS) (8.192 MHz) FP8i (GCI-Bus) (8 kHz) C8i (GCI-Bus) (8.192 MHz)
Channel 0 Channel 1
Data Sheet
Channel 510
Channel 511
BSTi/LSTi0-7 (32 Mbps) ST-BUS BSTi/LSTi0-7 (32 Mbps) GCI-Bus BSTi/LSTi0-15 (16 Mbps) ST-BUS BSTi/LSTi0-15 (16 Mbps) GCI-Bus BSTi/LSTi0-15 (8 Mbps) ST-BUS BSTi/LSTi0-15 (8 Mbps) GCI-Bus
32107654321076543210
65432107654321076 Channel 510 Channel 511
Channel 0
Channel 1
45670123456701234567
12345670123456701 Channel 255
Channel 0 1 0 7 6 5 4 3 2 1 0 6 5
4
3
2
1
0
7
Channel 0 6 7 0 1 2 3 4 5 6 7 1 2
Channel 255 3 4 5 6 7 0
Channel 0 0 7 6 Channel 0 7 0 1 Channel 0 2 3 4 5 4 3
Channel 127 2 1 0 7
Channel 127 5 6 7 0
Channel 63 6 1 Channel 63 1 6 Channel 31 0 Channel 31 7 0 7 7 0 0 7
BSTi/LSTi0-15 (4 Mbps) ST-BUS 0 BSTi/LSTi0-15 (4 Mbps) GCI-Bus 7 BSTi/LSTi0-15 (2 Mbps) ST-BUS 0 BSTi/LSTi0-15 (2 Mbps) GCI-Bus 7
7 Channel 0 0 Channel 0 7 Channel 0 0
Figure 6 - ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates
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Zarlink Semiconductor Inc.
ZL50050
2.3 Input Frame Pulse and Generated Frame Pulse Alignment
Data Sheet
The ZL50050 accepts a frame pulse (FP8i) and generates two frame pulse outputs, FP8o and FP16o, which are aligned to the master frame pulse. There is a constant throughput delay for data being switched from the input to the output of the device such that data which is input during Frame N is output during Frame N+2. For further details of frame pulse conditions and options, see Section 14.1, Control Register (CR), Figure 22, Frame Boundary Conditions, ST-BUS Operation, and Figure 23, Frame Boundary Conditions, GCI-Bus Operation.
FP8i C8i BSTi/LSTi0-15 (2 Mbps) BSTi/LSTi0-15 (4 Mbps) BSTi/LSTi0-15 (8 Mbps) BSTi/LSTi0-15 (16 Mbps) BSTi/LSTi0-7 (32 Mbps) FP8o C8o BSTo/LSTo0-15 (2 Mbps) BSTo/LSTo0-15 (4 Mbps) BSTo/LSTo0-15 (8 Mbps) BSTo/LSTo0-15 (16 Mbps) BSTo/LSTo0-7 (32Mbps)
CH0 CH0 CH0
CH 0
CH 01
CH0 CH0 CH0
CH 0
CH 01
CH1 CH1 CH2 CH4
CH 7 CH 8 CH 9
CH2 CH3 CH4 CH7
CH 13 CH 14 CH 15
CH5 CH9 CH10
CH 20 CH 21
CH1
CH 1 CH
2
CH2
CH 3 CH 4 CH 5
CH3
CH 6
CH5
CH 10 CH 11
CH6
CH 12
CH8
CH 16 CH 17
CH11
CH 22 CH 23
CH 18
CH 19
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
tFBOS
CH1 CH1 CH2 CH4
CH 7 CH 8 CH 9
CH2 CH3 CH4 CH7
CH 13 CH 14 CH 15
CH5 CH9
CH 19
CH1
CH 1 CH 2 CH 3
CH2
CH 4 CH 5
CH3
CH 6
CH5
CH 10 CH 11
CH6
CH 12
CH8
CH 16
CH10
CH 20
CH11
CH 23
CH CH 17 18
CH CH 21 22
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Figure 7 - Input and Output (Generated) Frame Pulse Alignment for Different Data Rates The tFBOS is the offset between the input frame pulse, FP8i, and the generated output frame pulse, FP8o. Refer to the "AC Electrical Characteristics," on page 80. Note that although the figure above shows the traditional setups of the frame pulses and clocks for both ST-BUS and GCI-Bus configurations, the devices can be configured to accept/generate double-width frame pulses (if the FPW bit in the Control Register is set) as well as to use the opposite clock edge for frame-boundary determination (using the C8IPOL and COPOL bits in the Control Register). See the timing diagrams in "AC Electrical Characteristics," on page 80 for all of the available configurations.
2.4
Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator
To improve the jitter tolerance of the ZL50050, a Frame Boundary Discriminator (FBD) circuit was added to the device. This circuit is enabled by setting the Control Register bit FBDEN to HIGH. By default the FBD is disabled. The FBD can operate in two modes, as controlled by the FBD_MODE[2:0] bits of the Control Register. When bits FBD_MODE[2:0] are set to 000B, the FBD is set to handle lower frequency jitter only (<8 kHz). When bits FBD_MODE[2:0] are set to 111B, the FBD can handle both low frequency and high frequency jitter. All other values are reserved. These bits are ignored when bit FBDEN is LOW. It is strongly recommended that if bit FBDEN is set HIGH, bits FBD_MODE[2:0] should be set to 111B to improve the high frequency jitter handling capability. To achieve the best jitter tolerance performance, it is also recommended that the input data sampling point be optimized. In most applications, the optimum sampling point is 1/2 instead of the default 3/4 (it can be changed by programming all the LIDR and BIDR registers). This will give more allowance for sampling point variations caused
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ZL50050
Data Sheet
by jitter. There are, however, some cases where data experience more delay than the timing signals. A common example is when multiple data lines are tied together to form bidirectional buses. The large bus loading may cause data to be delayed. If this is the case, the optimum sampling point may be 3/4 or 4/4 instead of 1/2. The optimum sampling point is dependent on the application. The user should optimize the sampling point to achieve the best jitter tolerance performance.
2.5
Input Clock Jitter Tolerance
Input clock jitter tolerance depends on the data rate. In general, the higher the data rate, the smaller the jitter tolerance is, because the period of a bit cell is shorter, and the sampling point variation allowance is smaller. Jitter tolerance can not be accurately represented by just one number. Jitter of the same amplitude but different frequency spectrum can have different effect on the operation of a device. For example, a device that can tolerate 20 ns of jitter of 10 kHz frequency may only be able to tolerate 10 ns of jitter of 1 MHz frequency. Therefore, jitter tolerance should be represented as a spectrum over frequency. The highest possible jitter frequency is half of the carrier frequency. In the case of the ZL50050, the input clock is 8.192 MHz, and the jitter associated with this clock can have the highest frequency component at 4.096 MHz. For the above reasons, jitter tolerance of the ZL50050 has been characterized at two data rates, 16.384 Mbps and 32.768 Mbps. The lower data rates (2.048Mbps, 4.096 Mbps, 8.192 Mbps) will have the same or better tolerance than that of the 16.384 Mbps operation. Tolerance of jitter of different frequencies are shown in the "AC Electrical Characteristics" section, table "Input Clock Jitter Tolerance" on page 90. The Jitter Tolerance Improvement Circuit was enabled (Control Register, bit FBDEN set HIGH, and bits FBD_MODE[2:0] set to 111B), and the sampling point was optimized.
2.6
Backward Compatibility with MT90871
The ZL50050 is pin-to-pin compatible with Zarlink's MT90871 device. To ensure software compatibility between the two devices, the user must consider the following items: 1. The ZL50050 has enhanced input clock jitter tolerance. To maximize the jitter tolerance, the Frame Boundary Discriminator (FBD) circuit has to be enabled by setting bits FBDEN and FBD_MODE[2:0] in the Control Register HIGH. In MT90871, these bits are un-used. The input data sampling point also needs to be optimized by programming all the LIDR and BIDR registers. These are described in details in Section 2.4. 2. When Bit Error Rate (BER) transmission is enabled, all the channels on all same side (Local/Backplane) as the target BER transmission channel(s) will be unable to switch traffic. Also, the BER Counters (LBCR and BBCR) will not rollover. They will saturate when they reach their maximum value. These are described in more details in Section 6.0. 3. The hardware reset signal (RESET) must be de-asserted less than 12 s after the frame boundary or more than 13s after the frame boundary, as described in Section 8.3. This can be achieved, for example, by synchronizing the de-assertion of the reset signal with the input frame pulse.
3.0
Input and Output Offset Programming
Various registers are used to control the input sampling point (delay) and the output advancement for the Local and Backplane streams. The following sections explain the details of these offset programming features.
3.1
Input Offsets
Control of the Input Channel Delay and the Input Bit Delay allows each input stream to have a different frame boundary with respect to the master frame pulse, FP8i. The use of Input Channel Delay in combination with Input Bit Delay enables the Ch0 position to be placed anywhere within a frame to a resolution of 1/4 of the bit period.
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3.1.1 Input Channel Delay Programming (Backplane and Local Input Streams)
Data Sheet
By programming the Backplane or Local Input Channel Delay Registers (BCDR0 - BCDR15 and LCDR0 LCDR15), users can individually assign the Ch0 position of each input stream to be located at any of the channel boundaries in a frame. For delays within channel boundaries, the input bit delay programming can be used. By default, all input streams have a channel delay of zero such that Ch0 is the first channel that appears after the frame boundary.
FP8i C8i
Ch 0 Ch 1 Ch126 Ch127
BSTi/LSTi0-15 Channel Delay = 0 (Default)
32107654321076543210 Channel Delay,1 Ch127
65432107654321076
Ch 0
Ch125
Ch126
BSTi/LSTi0-15 Channel Delay = 1
32107654321076543210
65432107654321076
Ch126
Channel Delay, 2 Ch127
Ch0
Ch125 7654321076
BSTi/LSTi0-15 Channel Delay = 2
3210765432107654321076543210
Figure 8 - Backplane and Local Input Channel Delay Timing Diagram (assuming 8 Mbps operation)
3.1.2
Input Bit Delay Programming (Backplane and Local Input Streams)
In addition to the Input Channel Delay programming, Input Bit Delay Registers LIDR0 - 15 and BIDR0 - 15 work in conjunction with the SMPL_MODE bit in the Control Register to allow users to control input bit fractional delay as well as input bit sample point selection for greater flexibility when designing switch matrices for high speed operation. When SMPL_MODE = LOW (input bit fractional delay mode), bits LID[4:0] and BID[4:0] in the LIDR0 - 15 and BIDR0 - 15 registers respectively define the input bit fractional delay of the corresponding local and backplane stream. The total delay can be up to 7 3/4 bits with a resolution of 1/4 bit at the selected data rate. When SMPL_MODE = HIGH (sampling point select mode), bits LID[1:0] and BID[1:0] define the input bit sampling point of the stream. The sampling point can be programmed at the 3/4, 4/4, 1/4 or 2/4 bit location to allow better tolerance for input jitter. Bits LID[4:2] and BID[4:2] define the integer input bit delay, with a maximum value of 7 bits at a resolution of 1 bit. Refer to Figure 9 and Figure 10 for Input Bit Delay Timing at 16 Mbps and 8 Mbps data rates, respectively. Refer to Figure 10 for Input Sampling Point Selection Timing at 8 Mbps data rates.
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SMPL_MODE = LOW
FP8i C8i
Ch255 Ch0 1 0 7 6 5 4 3 2 1 0 7 6 Ch1 5 4
Data Sheet
BSTi/LSTi0-15 Bit Delay = 0 (Default) BSTi/LSTi0-15 Bit Delay = 1/4
3
2
Bit Delay, 1/4 Ch255 3 2 1 0 7 6 5 Ch0 4 3 2 1 0 7 6 Ch1 5 4
Bit Delay, 1/2
BSTi/LSTi0-15 Bit Delay = 1/2
Ch255 3 2 1 0 7 6 5
Ch0 4 3 2 1 0 7 6
Ch1 5 4
Bit Delay, 3/4
BSTi/LSTi0-15 Bit Delay = 3/4
Ch255 3 2 1 0 7 6 5
Ch0 4 3 2 1 0 7 6
Ch1 5 4
Bit Delay, 1
BSTi/LSTi0-15 Bit Delay = 1
Ch255 3 2 1 0 7 6 5
Ch0 4 3 2 1 0 7 6
Ch1 5
BSTi/LSTi0-15 Bit Delay = 7 1/2
Ch254 2 1 0 7 6 5
Ch255 4 3 2 1 0 7
Bit Delay, 7 1/2 Ch0 6 5 4
BSTi/LSTi0-15 Bit Delay = 7 3/4
Ch254 2 1 0 7 6 5
Ch255 4 3 2 1 0 7
Bit Delay, 7 3/4 Ch0 6 5 4
Please refer to Control Register (Section 14.1) for SMPL_MODE definition.
Figure 9 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mbps
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Zarlink Semiconductor Inc.
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SMPL_MODE = LOW
FP8i C8i
Ch127 Ch0 0 7 6 5 4 3 2
Data Sheet
BSTi/LSTi0-15 BID[4:0]/LID[4:0] = 00000B Bit delay = 0 bit (Default) BSTi/LSTi0-15 BID[4:0]/LID[4:0] = 00011B Bit Delay = 3/4 bit
1
sample at 3/4 point Ch127 1 0 7 Ch0 6 sample at 3/4 point 5 4 3 2
SMPL_MODE = HIGH
FP8i C8i
Ch127 Ch0 0 7 6 sample at 3/4 point Ch127 Ch0 0 7 6 sample at 2/4 point 5 4 3 2 5 4 3 2
BSTi/LSTi0-15 BID[4:0]/LID[4:0] = 00000B 3/4 sampling (Default) BSTi/LSTi0-15 BID[4:0]/LID[4:0] = 00011B 2/4 sampling
1
1
Please refer to Control Register (Section 14.1) for SMPL_MODE definition.
Figure 10 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for Data Rate of 8 Mbps
3.2
Output Advancement Programming (Backplane and Local Output Streams)
This feature is used to advance the output channel alignment of individual Local or Backplane output streams with respect to the frame boundary FP8o. Each output stream has its own advancement value that can be programmed by the Output Advancement Registers. The output advancement selection is useful in compensating for various parasitic loading on the serial data output pins. The Local and Backplane Output Advancement Registers, LOAR0 - LOAR15 and BOAR0 - BOAR15, are used to control the Local and Backplane output advancement respectively. The advancement is determined with reference to the internal system clock rate (131.072 MHz). For 2 Mbps, 4 Mbps, 8 Mbps or 16 Mbps streams, the advancement can be 0, -2 cycles, -4 cycles or -6 cycles, which converts to approximately 0 ns, -15 ns, -31 ns or -46 ns as shown in Figure 11. For 32 Mbps streams, the advancement can be 0, -1 cycle, -2 cycles or -3 cycles, which converts to approximately 0ns, -7.6 ns, -15 ns or -23 ns.
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Zarlink Semiconductor Inc.
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Data Sheet
FP8o System Clock 131.072 MHz
Ch255
Bit Advancement, 0 Bit 0 Bit 7 Bit Advancement, -2 Bit 6 Ch0 Bit 6 Ch0 Bit 6 Ch0
Ch0 Bit 5
BSTo/LSTo0-15 Bit Advancement = 0 (Default) BSTo/LSTo0-15 Bit Advancement = -2 BSTo/LSTo0-15 Bit Advancement = -4 BSTo/LSTo0-15 Bit Advancement = -6
Bit 1
Bit 1 Ch255 Bit 0 Ch255 Bit 1 Ch255 Bit 1 Bit 0 Bit 0
Bit 7 Bit Advancement, -4 Bit 7 Bit Advancement, -6 Bit 7 Bit 6
Bit 5
Bit 5
Bit 4
Bit 5
Bit 4
Figure 11 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 16 Mbps
4.0
Port High-Impedance Control
The input pins, LORS and BORS, select whether the Local (LSTo0-15) and Backplane (BSTo0-15) output streams, respectively, are set to high impedance at the output of the device itself, or are always driven (active HIGH or active LOW). In the latter case (i.e., always driven), a high impedance state, if required on a per-channel basis, is invoked through an external interface circuit controlled by the LCSTo0-1/BCSTo0-1 signals. Setting LORS/BORS to a LOW state will configure the output streams, LSTo0-15/BSTo0-15, to transmit bi-state channel data with per-channel high impedance determined by external circuits under the control of the LCSTo0-1/BCSTo0-1 outputs. Setting LORS/BORS to a HIGH state will configure the output streams, LSTo0-15/BSTo0-15, of the device to invoke a high impedance output on a per-channel basis when required as controlled by the LE/BE bit. The state of the LORS/BORS pin is detected and the device configured accordingly during a RESET operation, e.g., following power-up. The LORS/BORS pin is an asynchronous input and is expected to be hard-wired for a particular system application, although it may be driven under logic control if preferred. The Local/Backplane output enable control in order of highest priority is: RESET, ODE, OSB, LE/BE. LE/BE OSB (Local / LORS/BORS (Control Backplane (input pin) Register bit) Connection Memory bit) X X X X 0 0 1 X X X X X X 0 0 1 0 1 0 1 0
RESET (input pin)
ODE (input pin)
LSTo0-15/ BSTo0-15
LCSTo0-1/ BCSTo0-1
0 0 1 1 1 1 1
X X 0 0 1 1 1
HIGH HI-Z HIGH HI-Z HIGH HI-Z HIGH
LOW LOW LOW LOW LOW LOW LOW
Table 2 - Local and Backplane Output Enable Control Priority
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LE/BE OSB (Local / LORS/BORS (Control Backplane (input pin) Register bit) Connection Memory bit) 1 1 0 1 1 X
Data Sheet
RESET (input pin)
ODE (input pin)
LSTo0-15/ BSTo0-15
LCSTo0-1/ BCSTo0-1
1 1
1 1
HI-Z
LOW
ACTIVE ACTIVE (HIGH or LOW) (HIGH or LOW)
Table 2 - Local and Backplane Output Enable Control Priority (continued)
4.1
LORS/BORS Asserted LOW, Non-32Mbps Mode
The data (channel control bit) transmitted by L/BCSTo0-1 replicates the Local/Backplane Output Enable (LE/BE) bit of the Local/Backplane Connection Memory, with a LOW state indicating the channel to be set to high impedance. Refer to "Local Connection Memory Bit Definition," on page 49 and "Backplane Connection Memory Bit Definition," on page 50 for more details. The L/BCSTo0-1 pins transmit serial data (channel control bits) at 16.384 Mbps, with each bit representing the per-channel high impedance state for a specific stream. Eight output streams are allocated to each control line as follows: * * L/BCSTo0 outputs the channel control bits for streams L/BSTo0, 2, 4, 6, 8, 10, 12, and 14 L/BCSTo1 outputs the channel control bits for streams L/BSTo1, 3, 5, 7, 9, 11, 13, and 15
The channel control bit location, within a frame period, for each channel of the Local/Backplane output streams is presented in Table 3, L/BCSTo Allocation of Channel Control Bits to Output Streams (Non-32 Mbps Mode). As an aid to the description, the channel control bit for a single channel on specific streams is presented, with reference to Table 3: 1. The channel control bit corresponding to Stream 0, Channel 0, L/BSTo0_Ch0, is transmitted on L/BCSTo0 and is advanced, relative to the frame boundary, by 10 periods of C16o. 2. The channel control bit corresponding to Stream 14, Channel 0, L/BSTo14_Ch0, is transmitted on L/BCSTo0 in advance of the frame boundary by three periods of output clock, C16o. Similarly, the channel control bits for L/BSTo15_Ch0 are advanced relative to the frame boundary by three periods of C16o on L/BCSTo1. The L/BCSTo0-1 pins output data at a constant data rate of 16.384 Mbps, independent of the data rate selected for the individual output streams, L/BSTo0-15. Streams at data rates lower than 16.384 Mbps will have the value of their respective channel control bit repeated for the duration of the channel. The bit will be repeated twice for 8.192 Mbps streams, four times for 4.096 Mbps streams and eight times for 2.048 Mbps streams. The channel control bit is not repeated for 16.384 Mbps streams. Examples are presented, with reference to Table 3: 3. With stream L/BSTo2 selected to operate at a data rate of 2.048 Mbps, the value of the channel control bit for Channel 0 will be transmitted during the C16o clock period numbers 2040, 2048, 8, 16, 24, 32, 40 and 48. 4. With stream L/BSTo4 operated at a data rate of 8.192 Mbps, the value of the channel control bit for Channel 1 will be transmitted during the C16o clock period numbers 9 and 17.
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Allocated Stream No. C16o Period1 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 etc. etc. 2029 2030 2031 2032 2033 2034 2035 2 4 2 4 2 L/BCSTo0 0 3-1 2
3-3
Data Sheet
Channel No. 2 16 Mbps Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 2 Ch 2 Ch 2 Ch 2 Ch 2 Ch 2 Ch 2 Ch 2 Ch 3 Ch 3 Ch 3 etc. etc. Ch 254 Ch 254 Ch 255 Ch 255 Ch 255 Ch 255 Ch 255 8 Mbps Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 etc. etc. Ch 127 Ch 127 Ch 127 Ch 127 Ch 127 Ch 127 Ch 127 4 Mbps Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 etc. etc. Ch 63 Ch 63 Ch 63 Ch 63 Ch 63 Ch 63 Ch 63 2 Mbps Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 etc. etc. Ch 31 Ch 31 Ch 31 Ch 31 Ch 31 Ch 31 Ch 31 Frame Boundary
L/BCSTo1 1 3 5 7 9 11 13 15 3-2 1 3 5 7 9 11 13 15 1 3 5 7 9 11 13 15 1 3 5 etc. etc. etc. 15 1 3 5 7 9
4 6 8 10 12 14 3-2 0
3-3
4 6 8 10 12 14 0
3-3 3-4
6 8 10 12 14 0
3-3 3-4
etc. etc. etc. 14 0 2 4 6 8
Table 3 - L/BCSTo Allocation of Channel Control Bits to Output Streams (Non-32 Mbps Mode)
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Allocated Stream No. C16o Period1 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 1 2 3 etc. 2 L/BCSTo0 10 12 14 0 2
3-1 3-3
Data Sheet
Channel No. 2 16 Mbps Ch 255 Ch 255 Ch 255 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 etc. 8 Mbps Ch 127 Ch 127 Ch 127 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 etc. 4 Mbps Ch 63 Ch 63 Ch 63 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 etc. 2 Mbps Ch 31 Ch 31 Ch 31 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 etc. Frame Boundary
L/BCSTo1 11 13 15 1 3 5 7 9 11 13 15
3-2
4 6 8 10 12 14
3-2
0
3-3
1 3 5 7 9 etc.
4 6 8 etc.
Table 3 - L/BCSTo Allocation of Channel Control Bits to Output Streams (Non-32 Mbps Mode) (continued)
Note 1: Note 2: Note 3: Clock period count is referenced to frame boundary. The channel numbers presented relate to the data rate selected for a specific stream. 3-1 to 3-4: See above for examples of channel control bits for streams of different data rates.
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Data Sheet
Figure 12, Local/Backplane Port External High-Impedance Control Bit Timing (Non-32 Mbps Mode) shows the channel control bits for L/BCSTo0 and L/BCSTo1 in one possible scenario which includes stream L/BSTo0 at a data rate of 16.384 Mbps, L/BSTo1 at 8.192 Mbps, L/BSTo6 at 4.096 Mbps and L/BSTo7 at 2.048 Mbps. All remaining streams are operated at a data rate of 16.384 Mbps.
FP8o C8o
Channel 255 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
Channel 0
L/BSTo0 (16 Mbps) L/BSTo1 (8 Mbps) L/BSTo6 (4 Mbps) L/BSTo7 (2 Mbps)
1
0
7
6
5
Chan 127 Bit 0
Chan 0 Bit 7
Chan 0 Bit 6
Chan 0 Bit 5
Chan 0 Bit 4
Chan 127 Chan 127 Chan 127 Chan 127 Bit 3 Bit 2 Bit 1 Bit 0
Chan 0 Bit 7
Chan 63 Bit 0 Chan 31 Bit 0
Chan 0 Bit 7
Chan 0 Bit 6
Chan 63 Bit 1
Chan 63 Bit 0
Chan 0 Bit 7 Chan 0 Bit 7
Channel 0 Bit 7
Channel 31 Bit 0
CH 0 L/BSTo10
CH 0 L/BSTo12
CH 1 L/BSTo10
CH 1 L/BSTo12
CH 1 L/BSTo14
CH 0 L/BSTo14
CH 0 L/BSTo4
CH 0 L/BSTo6
CH 0 L/BSTo8
CH 1 L/BSTo0
CH 1 L/BSTo2
CH 1 L/BSTo4 CH 1 L/BSTo5
CH 1 L/BSTo0
CH 1 L/BSTo2
CH 1 L/BSTo4
CH 0 L/BSTo6
CH 1 L/BSTo8
CH 2 L/BSTo0
L/BCSTo0
CH 2 L/BST02
CH 0 L/BSTo11
CH 0 L/BSTo13
CH 1 L/BSTo11
CH 1 L/BSTo13
CH 1 L/BSTo15
CH 0 L/BSTo15
CH 0 L/BSTo5
CH 0 L/BSTo7
CH 0 L/BSTo9
CH 0 L/BSTo1
CH 1 L/BSTo3
CH 0 L/BSTo1
CH 1 L/BSTo3
CH 1 L/BSTo5
CH 0 L/BSTo7
CH 1 L/BSTo9
CH 1 L/BSTo1
L/BCSTo1
CH 2 L/BSTo3
One C16o period
Figure 12 - Local/Backplane Port External High-Impedance Control Bit Timing (Non-32 Mbps Mode)
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Zarlink Semiconductor Inc.
CH 0 L/BSTo7
CH 0 L/BSTo6
ZL50050
4.2 LORS/BORS Asserted LOW, 32 Mbps Mode
Data Sheet
Note that when the devices are operating in Local or Backplane 32 Mbps mode, some of the output streams (the upper half of the available streams) are unused. The LE/BE bits of the channels on those output streams will always be low. Therefore, the upper LSTo/BSTo pins are either driven HIGH or high impedance, in accordance with the value of the LORS/BORS input signals, as shown in Table 2 on page 30. The data (channel control bit) transmitted by L/BCSTo0-1 replicates the Local/Backplane Output Enable (LE/BE) bit of the Local/Backplane Connection Memory, with a LOW state indicating the channel to be set to high impedance. Refer to "Local Connection Memory Bit Definition," on page 49 and "Backplane Connection Memory Bit Definition," on page 50 for more details. The L/BCSTo0-1 pins transmit serial data (channel control bits) at 16.384 Mbps, with each bit representing the per-channel high impedance state for a specific stream. Four output streams are allocated to each control line as follows: * * L/BCSTo0 outputs the channel control bits for streams L/BSTo0, 2, 4, and 6 L/BCSTo1 outputs the channel control bits for streams L/BSTo1, 3, 5, and 7
The channel control bit location, within a frame period, for each channel of the Local/Backplane output streams is presented in Table 4, L/BCSTo Allocation of Channel Control Bits to Output Streams (32 Mbps Mode) The L/BCSTo0-1 pins output data at a constant data rate of 16.384 Mbps and all output streams, L/BSTo0-7, operate at a data rate of 32.768 Mbps. As an aid to the description, the channel control bit for a single channel on specific streams is presented, with reference to Table 4: 1. The channel control bit corresponding to Stream 0, Channel 0, L/BSTo0_Ch0, is transmitted on L/BCSTo0 and is advanced, relative to the frame boundary, by ten periods (clock period number 2039) of C16o. 2. The channel control bit corresponding to Stream 6, Channel 0, L/BSTo6_Ch0, is transmitted on L/BCSTo0 in advance of the frame boundary by seven periods (clock period number 2042) of output clock, C16o. Similarly, the channel control bits for L/BSTo7_Ch0 are advanced relative to the frame boundary by seven periods of C16o on L/BCSTo1. 3. For stream L/BSTo2, the value of the channel control bit for Channel 511 will be transmitted during the C16o clock period number 2036 on L/BCSTo0. 4. For stream L/BSTo3, the value of the channel control bit for Channel 5 will be transmitted during the C16o clock period number 12 on L/BCSTo1.
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Zarlink Semiconductor Inc.
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Allocated Stream No. C16o Period1 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 etc. etc. 2029 2030 2031 2032 2033 2034 6 L/BCSTo0 0 3-1 2 4
3-2
Data Sheet
Channel No. 2 32 Mbps Ch 0 Ch 0 Ch 0 Ch 0 Ch 1 Ch 1 Ch 1 Ch 1 Ch 2 Ch 2 Ch 2 Ch 2 Ch 3 Ch 3 Ch 3 Ch 3 Ch 4 Ch 4 Ch 4 Ch 4 Ch 5 Ch 5 Ch 5 Ch 5 Ch 6 Ch 6 Ch 6 etc. etc. Ch 509 Ch 509 Ch 510 Ch 510 Ch 510 Ch 510 Frame Boundary
L/BCSTo1 1 3 5 7
3-2
0 2 4 6 0 2 4 6 0 2 4 6 0 2 4 6 0 2 4 6 0 2 4 etc. etc. etc. 6 0 2 4 6 3
1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1
3-4
5 7 1 3 5 etc. etc. etc. 7 1 3 5 7
Table 4 - L/BCSTo Allocation of Channel Control Bits to Output Streams (32 Mbps Mode)
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Allocated Stream No. C16o Period1 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 1 2 3 etc. 0 2 L/BCSTo0 0
3-3
Data Sheet
Channel No. 2 32 Mbps Ch 511 Ch 511 Ch 511 Ch 511 Ch 0 Ch 0 Ch 0 Ch 0 Ch 1 Ch 1 Ch 1 Ch 1 Ch 2 Ch 2 Ch 2 Ch 2 Ch 3 etc. Frame Boundary
L/BCSTo1 1 3 5 7 1 3 5 7 3-2 1 3 5 7 1 3 5 7 1 etc.
4 6
3-1
2 4 6 3-2 0 2 4 6 0 2 4 6 0 etc.
Table 4 - L/BCSTo Allocation of Channel Control Bits to Output Streams (32 Mbps Mode) (continued)
Note 1: Note 2: Note 3: Clock period count is referenced to frame boundary. The channel numbers presented relate to the specific stream operating at a data rate of 32.768 Mbps. 3-1 to 3-4: See above for examples of channel control bits.
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Data Sheet
Figure 13, Local and Backplane Port External High-Impedance Control Timing (32 Mbps Mode) shows the channel control bits for L/BCSTo0 and L/BCSTo1.
FP8o
C8o
L/BSTo0 (32 Mbps) L/BSTo1 (32 Mbps) L/BSTo2 (32 Mbs) L/BSTo3 (32 Mbps)
Channel 0 bits 7-0 Channel 0 bits 7-0 Channel 0 bits 7-0 Channel 0 bits 7-0
Channel 1 bits 7-0 Channel 1 bits 7-0 Channel 1 bits 7-0 Channel 1 bits 7-0
Channel 510 bits 7-0 Channel 510 bits 7-0 Channel 510 bits 7-0 Channel 510 bits 7-0
Channel 511 bits 7-0 Channel 511 bits 7-0 Channel 511 bits 7-0 Channel 511 bits 7-0
CH 0 L/BSTo4
CH 0 L/BSTo6
CH 1 L/BSTo0
CH 1 L/BSTo2
CH 1 L/BSTo4
CH 1 L/BSTo6
CH 2 L/BSTo0
CH 2 L/BSTo2
CH 2 L/BSTo4 CH 2 L/BSTo5
CH 2 L/BSTo0
CH 2 L/BSTo2
CH 2 L/BSTo4
CH 2 L/BSTo6
CH 3 L/BSTo0
CH 3 L/BSTo2
CH 3 L/BSTo4
CH 3 L/BSTo6
CH 4 L/BSTo0
CH 0 L/BSTo5
CH 0 L/BSTo7
CH 1 L/BSTo1
CH 1 L/BSTo3
CH 1 L/BSTo5
CH 1 L/BSTo7
CH 2 L/BSTo1
CH 2 L/BSTo3
CH 2 L/BSTo1
CH 2 L/BSTo3
CH 2 L/BSTo5
CH 2 L/BSTo7
CH 3 L/BSTo1
CH 3 L/BSTo3
CH 3 L/BSTo5
CH 3 L/BSTo7
CH 4 L/BSTo1
CH 4 L/BSTo3
One C16o cycle
Figure 13 - Local and Backplane Port External High-Impedance Control Timing (32 Mbps Mode)
4.3
LORS/BORS Asserted HIGH
When the LORS/BORS input pin is HIGH, the Local/Backplane Output Enable Bit (LE/BE) of the Local/Backplane Connection Memory has direct per-channel control on the high impedance state of the Local/Backplane output streams, L/BSTo0-15. Programming a LOW state in the connection memory LE/BE bit will set the stream output of the device to high impedance for the duration of the channel period. See "Local Connection Memory Bit Definition," on page 49 and "Backplane Connection Memory Bit Definition," on page 50 for programming details. When the LORS/BORS signal is asserted HIGH, the L/BCSTo0-1 outputs directly the values given in LE/BE.
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Zarlink Semiconductor Inc.
CH 2 L/BSTo7
L/BCSTo1
CH 4 L/BSTo2
CH 2 L/BSTo6
L/BCSTo0
ZL50050
5.0 Data Delay Through the Switching Paths
Data Sheet
Serial data which goes into the device is converted into parallel format and written to consecutive locations in the data memory. Each data memory location corresponds to the input stream and channel number. With the input channel delay feature disabled, channels written to any of the buffers during Frame N will be read out during Frame N+2. With the input channel delay feature enabled, channels written to any of the buffers during Frame N will be read out during Frame N+3. The input channel offsets affect the overall throughput delay; however the input bit delay and output bit advancement have no impact on the overall data throughput delay. In the following paragraphs, the data throughput delay (T) is represented as a function of ST-BUS frames, input channel number, (m), output channel number (n), and input channel delay (). Table 5 describes the variable range for input streams and Table 6 describes the variable range for output streams. Table 7 summarizes the data throughput delay under various input channel and output channel delay conditions.
Input Stream Data Rate 2 Mbps 4 Mbps 8 Mbps 16 Mbps 32 Mbps
Input Channel Number (m) 0 to 31 0 to 63 0 to 127 0 to 255 0 to 511
Possible Input channel delay () 0 to 31 0 to 63 0 to 127 0 to 255 0 to 511
Table 5 - Variable Range for Input Streams
Output Stream Data Rate 2 Mbps 4 Mbps 8 Mbps 16 Mbps 32 Mbps
Output Channel Number (n) 0 to 31 0 to 63 0 to 127 0 to 255 0 to 511
Table 6 - Variable Range for Output Streams
Input Channel Delay OFF T = 2 frames + (n - m)
Input Channel Delay ON T = 3 frames - + (n - m)
Table 7 - Data Throughput Delay
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Data Sheet
By default, when the input channel delay, , is set to zero, the data throughput delay (T) is: T = 2 frames + (n - m). Assuming that m (input channel) and n (output channel) are equal, we have the figure below, in which the delay between the input data being written and the output data being read is exactly 2 frames.
Frame Serial Input Data (No Delay) Serial Output Data (No Delay)
Frame N
Frame N+1
Frame N+2
Frame N+3
Frame N+4
Frame N+5
Frame N Data
Frame N+1Data 2 Frames + 0
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
Frame N+5 Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
Figure 14 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch0 Switched to Output Ch0 Assuming that n (output channel) is greater than m (input channel), we have the figure below, in which the delay time between the input channel being written and the output channel being read exceeds 2 frames.
Frame Serial Input Data (No Delay) Serial Output Data (No Delay)
Frame N
Frame N+1
Frame N+2
Frame N+3
Frame N+4
Frame N+5
Frame N Data
Frame N+1Data
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
Frame N+5 Data
2 Frames + (n - m) Frame N-2 Data Frame N-1 Data Frame N Data Frame N+1 Data Frame N+2 Data Frame N+3 Data
Figure 15 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch0 Switched to Output Ch13 Assuming that n (output channel) is less than m (input channel), we have the figure below, in which the delay time between the input channel being written and the output channel being read is less than 2 frames.
Frame Serial Input Data (No Delay)
Frame N
Frame N+1
Frame N+2
Frame N+3
Frame N+4
Frame N+5
Frame N Data
Frame N+1Data
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
Frame N+5 Data
2 Frames + (n - m)
Serial Output Data (No Delay)
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
Figure 16 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch13 Switched to Output Ch0
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Data Sheet
When the input channel delay is enabled, the data throughput delay is: T = 3 frames - + (m - n). Assuming that m (input channel) and n (output channel) are equal, we have the figure below, in which the delay between the input data being written and the output data being read is less than 3 frames.
Frame
Frame N
Frame N+1
Frame N+2
Frame N+3
Frame N+4
Frame N+5
Input Channel Delay (from 1 to max # of channels)
Serial Input Data ( > 0)
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
3 Frames - + 0
Serial Output Data
Frame N-3 Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Figure 17 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch0 Switched to Output Ch0 Assuming that n (output channel) is greater than m (input channel), we have the figure below, in which the delay time between the input channel being written and the output channel being read could exceed 3 frames, if the distance between n and m is greater than the input channel delay.
Frame
Frame N
Frame N+1
Frame N+2
Frame N+3
Frame N+4
Frame N+5
Input Channel Delay (from 1 to max # of channels)
Serial Input Data ( > 0)
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
3 Frames - + (n - m)
Serial Output Data
Frame N-3 Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Figure 18 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch0 Switched to Output Ch13 Assuming that n (output channel) is less than m (input channel), we have the figure below, in which the delay time between the input channel being written and the output channel being read will be less than 3 frames.
Frame
Frame N
Frame N+1
Frame N+2
Frame N+3
Frame N+4
Frame N+5
Input Channel Delay (from 1 to max # of channels)
Serial Input Data ( > 0)
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
3 Frames - + (n - m)
Serial Output Data
Frame N-3 Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Figure 19 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch13 Switched to Output Ch0
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6.0 Bit Error Rate Test
Data Sheet
Independent Bit Error Rate (BER) testers are provided for the Local and Backplane ports. In both ports there is a BER transmitter and a BER receiver. The transmitter and receiver are each independently controlled to allow Backplane-to-Backplane, Local-to-Local, Backplane-to-Local, or Local-to-Backplane testing. The transmitter generates a 215-1 or 223-1 Pseudo Random Binary Sequence (PRBS), which may be allocated to a specific stream and number of channels. This is defined by a stream number, a start channel number, and the number of consecutive channels following the start channel. The stream, channel number and the number of consecutive channels following the start channel are similarly allocated for the receiver and detection of the PRBS. Examples of a channel sequence are presented in Figure 20.
frame boundary FP8i Start Ch=0 L/BTXB8-0=111111111B Total Length = 256 Channels Start Ch=0 L/BXTR8-0=000000001B Total Length = 3 Channels 0 1 2 3 ...... ..... ..... ..... 254 255 0 1 2
0
1
2
3
......
.....
.....
.....
254
255
0
1
2
Start Ch=254 L/BXTR8-0=000000011B Total Length = 4 Channels
0
1
2
3
......
.....
.....
.....
254
255
0
1
2
Channels containing PRBS sequence
Channels containing unknown data
Note: Total Length = Number of Consecutive Channels Desired Programmed in L/BTXR8-0 - 1 Channel Once started, BER transmission continues until stopped by the BER Control Register.
Figure 20 - Examples of BER Transmission Channels on a 16 Mbps Output Stream When enabled, the receiver attempts to lock to the PRBS on the incoming bit stream. Once lock is achieved, by detection of a seed value, a bit-by-bit comparison takes place and each error will increment a 16-bit counter. A counter saturation to FFFFH occurs in the event of an error count in excess of 65535. The BER operations are controlled by registers as follows (refer to Section 14.3, Bit Error Rate Test Control Register (BERCR) for overall control, Section 14.10, Local Bit Error Rate (BER) Registers and Section 14.11, Backplane Bit Error Rate (BER) Registers for register programming details): * * * * * * BER Control Register (BERCR) - Independently enables BER transmission and receive testing for Backplane and Local ports. Local and Backplane BER Start Send Registers (LBSSR and BBSSR) - Define the output stream and start channel for BER transmission. Local and Backplane Transmit BER Length Registers (LTXBLR and BTXBLR) - Define, for transmit stream, how many consecutive channels to follow the start channel. Local and Backplane BER Start Receive Registers (LBSR and BBSR) - Define the input stream and channel from which the BER sequence will start to be compared. Local and Backplane Receive BER Length Registers (LRXBLR and BRXBLR) - Define, for the receive stream, how many consecutive channels to follow the start channel. Local and Backplane BER Count Registers (LBCR and BBCR) - Contain the number of counted errors.
The registers listed completely define the transmit and receive stream and channels. When BER transmission is enabled for these channels, the source bits and the Message Mode bits, LSRC and LMM in the Local Connection Memory, and BSRC and BMM in the Backplane Connection Memory, are ignored. The per-channel enable bits (LE
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Data Sheet
and BE) of the respective connection memories should be set to HIGH to enable the outputs for the selected channels. The BER receive channel numbering is not affected by the input channel delay value. It means that the BER receive circuitry always assume there is no input channel delay, regardless of the values of the BCDR and LCDR registers. For example, if BER data is received on local input stream 0 channel 3, without input channel delay, the LBSRR (Local BER Start Receive Register) should be programmed to 3. With input channel delay of 5, however, the LBSRR should be programmed to 8 (3 + 5) instead. Note that when BER transmission is enabled, the target channels will carry PRBS data, and the rest of the channels on all streams of the same side (Local/Backplane) will carry unknown data, which renders that side of the switch unable to switch traffic during BER Test.
7.0
Microprocessor Port
The 16K switch family supports non-multiplexed Motorola type microprocessor buses. The microprocessor port consists of a 16-bit parallel data bus (D0-15), a 15-bit address bus (A0-14) and four control signals (CS, DS, R/W and DTA). The data bus provides access to the internal registers, the Backplane Connection and Data Memories, and the Local Connection and Data Memories. Each memory has 8,192 locations. See Table 11, Address Map for Data and Connection Memory Locations (A14 = 1), for the address mapping. Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can only be read (but not written) from the microprocessor port. To prevent the bus'hanging', in the event of the switch not receiving a master clock, the microprocessor port shall complete the DTA handshake when accessed, but any data read from the bus will be invalid.
8.0
8.1
Device Power-up, Initialization and Reset
Power-Up Sequence
The recommended power-up sequence is for the VDD_IO supply (nominally +3.3V ) to be established before the power-up of the VDD_PLL and VDD_CORE supplies (nominally +1.8V). The VDD_PLL and VDD_CORE supplies may be powered up simultaneously, but neither should 'lead' the VDD_IO supply by more than 0.3 V. All supplies may be powered-down simultaneously.
8.2
Initialization
Upon power up, the device should be initialized by applying the following sequence: 1. Ensure the TRST pin is permanently LOW to disable the JTAG TAP controller. 2. Set ODE pin to LOW. This configures the LCSTo0-1 output signals to LOW (i.e., setting optional external output buffers to high impedance), and sets the LSTo0-15 outputs to HIGH or high impedance, dependent on the LORS input value, and sets the BCSTo0-1 output signals to LOW (i.e., setting optional external output buffers to high impedance), and sets the BSTo0-15 outputs to HIGH or high impedance, dependent on BORS input value. Refer to Pin Description for details of the LORS and BORS pins. 3. Reset the device by asserting the RESET pin to zero for at least two cycles of the input clock, C8i. A delay of an additional 250 s must also be applied before the first microprocessor access is performed following the de-assertion of the RESET pin; this delay is required for determination of the input frame pulse format.
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Data Sheet
4. Use the Block Programming Mode to initialize the Local and the Backplane Connection Memories. Refer to Section 9.3, Connection Memory Block Programming. 5. Set ODE pin to HIGH after the connection memories are programmed to ensure that bus contention will not occur at the serial stream outputs.
8.3
Reset
The RESET pin is used to reset the device. When set LOW, an asynchronous reset is applied to the device. It is then synchronized to the internal clock. During the reset period, depending on the state of input pins LORS and BORS, the output streams LSTo0-15 and BSTo0-15 are set to HIGH or high impedance, and all internal registers and counters are reset to the default state. The RESET pin must remain LOW for two input clock cycles (C8i) to guarantee a synchronized reset release. A delay of an additional 250 s must also be waited before the first microprocessor access is performed following the de-assertion of the RESET pin; this delay is required for determination of the frame pulse format. In addition, the reset signal must be de-asserted less than 12 s after the frame boundary or more than 13 s after the frame boundary, as illustrated in Figure 21. This can be achieved, for example, by synchronizing the de-assertion of the reset signal with the input frame pulse FP8i.
FP8i RESET (case 1) RESET (case 2) 12 s RESET assertion 13 s RESET de-assertion
De-assertion of RESET must not fall within this window
Figure 21 - Hardware RESET De-assertion
9.0
Connection Memory
The device includes two connection memories, the Local Connection Memory and the Backplane Connection Memory.
9.1
Local Connection Memory
The Local Connection Memory (LCM) is a 16-bit wide memory with 4,096 memory locations to support the Local output port. The most significant bit of each word, bit[15], selects the source stream from either the Backplane (LSRC = LOW) or the Local (LSRC = HIGH) port and determines the Backplane-to-Local or Local-to-Local data routing. Bits[14:13] select the control modes of the Local output streams, the per-channel Message Mode and the per-channel high impedance output control modes. In Connection Mode (bit[14] = LOW), bits[12:0] select the source stream and channel number as detailed in Table 8. In Message Mode (bit[14] = HIGH), bits[12:8] are unused and bits[7:0] contain the message byte to be transmitted. Bit[13] must be HIGH for Message Mode to ensure that the output channel is not tri-stated.
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9.2 Backplane Connection Memory
Data Sheet
The Backplane Connection Memory (BCM) is a 16-bit wide memory with 4,096 memory locations to support the Backplane output port. The most significant bit of each word, bit[15], selects the source stream from either the Backplane (BSRC = HIGH) or the Local (BSRC = LOW) port and determines the Local-to-Backplane or Backplane-to-Backplane data routing. Bit[14:13] select the control modes of the Backplane output streams, namely the per-channel Message Mode and the per-channel high impedance output control mode. In Connection Mode (bit[14] = LOW), bits[12:0] select the source stream and channel number as detailed in Table 8. In Message Mode (bit[14] = HIGH), bits[12:8] are unused and bits[7:0] contain the message byte to be transmitted. Bit[13] must be HIGH for Message Mode to ensure that the output channel is not tri-stated. The Control Register bits MS[2:0] must be set to 000 to select the Local Connection Memory for the write and read operations via the microprocessor port. The Control Register bits MS[2:0] must be set to 001 to select the Backplane Connection Memory for the write and read operations via the microprocessor port. See Section 7.0, Microprocessor Port, and Section 14.1, Control Register (CR) for details on microprocessor port access. Source Stream Bit Rate 2 Mbps 4 Mbps 8 Mbps 16 Mbps 32 Mbps Source Stream No. Bits[12:8] legal values 0:31 Bits[12:8] legal values 0:31 Bits[12:8] legal values 0:31 Bits[12:8] legal values 0:31 Bits[12:9] legal values 0:15 Source Channel No. Bits[7:0] legal values 0:31 Bits[7:0] legal values 0:63 Bits[7:0] legal values 0:127 Bits[7:0] legal values 0:255 Bits[8:0] legal values 0:511
Table 8 - Local and Backplane Connection Memory Configuration
9.3
Connection Memory Block Programming
This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after power-up. When the Memory Block Programming mode is enabled, the contents of the Block Programming Register (BPR) will be loaded into the connection memories. See Table 19 and Table 20 for details of the Control Register and Block Programming Register values, respectively.
9.3.1
* *
Memory Block Programming Procedure:
Set the MBP bit in the Control Register from LOW to HIGH. Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits, LBPD[2:0], of the Block Programming Register, will be loaded into bits[15:13] of the Local Connection Memory. The remaining bit positions are loaded with zeros as shown in Table 9. 15 LBPD2 14 LBPD1 13 LBPD0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Table 9 - Local Connection Memory in Block Programming Mode
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Data Sheet
The Backplane Block Programming data bits, BBPD[2:0], of the Block Programming Register, will be loaded into bits[15:13] respectively, of the Backplane Connection Memory. The remaining bit positions are loaded with zeros as shown in Table 10. 15 BBPD2 14 BBPD1 13 BBPD0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Table 10 - Backplane Connection Memory in Block Programming Mode The Block Programming Register bit, BPE will be automatically reset LOW within 125 s, to indicate completion of memory programming. The Block Programming Mode can be terminated at any time prior to completion by clearing the BPE bit of the Block Programming Register or the MBP bit of the Control Register. Note that the default values (LOW) of LBPD[2:0] and BBPD[2:0] of the Block Programming Register, following a device reset, can be used. During reset, all output channels go HIGH or high impedance, depending on the value of the LORS and BORS pins, irrespective of the values in bits[14:13] of the connection memory.
10.0
Memory Built-In-Self-Test (BIST) Mode
As operation of the memory BIST will corrupt existing data, this test must only be instigated when the device is placed "out-of-service" or isolated from live traffic. The memory BIST mode is enabled through the microprocessor port (Section 14.14, Memory BIST Register). Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The memory test result is monitored through the Memory BIST Register.
11.0
JTAG Port
The ZL50050 JTAG interface conforms to the IEEE 1149.1 standard. The operation of the boundary-scan circuit shall be controlled by an external Test Access Port (TAP) Controller.
11.1
Test Access Port (TAP)
The Test Access Port (TAP) consists of four input pins and one output pin described as follows: * Test Clock Input (TCK) TCK provides the clock for the TAP Controller and is independent of any on-chip clock. TCK permits the shifting of test data into or out of the Boundary-Scan register cells under the control of the TAP Controller in Boundary-Scan Mode. Test Mode Select Input (TMS) The TAP controller uses the logic signals applied to the TMS input to control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin in internally pulled to VDD_IO when not driven from an external source. Test Data Input (TDi) Depending on the previously applied data to the TMS input, the serial input data applied to the TDi port is connected either to the Instruction Register or to a Test Data Register. Both registers are described in Section 11.2, TAP Registers. The applied input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to VDD_IO when not driven from an external source.
*
*
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*
Data Sheet
Test Data Output (TDo) Depending on the previously applied sequence to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDo. The data out of the TDo is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo output is set to a high impedance state. Test Reset (TRST) TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled high when not driven from an external source. This pin MUST be pulled low for normal operation.
*
11.2
TAP Registers
The ZL50050 implements the public instructions defined in the IEEE-1149.1 standard with the provision of an Instruction Register and three Test Data Registers.
11.2.1
Test Instruction Register
The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the Instruction Register from the TDi pin when the TAP Controller is in the shift-IR state. Instructions are subsequently decoded to achieve two basic functions: to select the Test Data Register to operate while the instruction is current, and to define the serial Test Data Register path to shift data between TDi and TDo during data register scanning. Please refer to Figure 33 for JTAG test port timing.
11.2.2 11.2.2.1
Test Data Registers The Boundary-Scan Register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the ZL50050 core logic.
11.2.2.2
The Bypass Register
The Bypass register is a single stage shift register to provide a one-bit path from TDi to TDo.
11.2.2.3
The Device Identification Register
The JTAG device ID for the ZL50050 is 0C38214BH. Version, Bits <31:28>:0000 Part No., Bits <27:12>:1100 0011 1000 0010 Manufacturer ID, Bits <11:1>:0001 0100 101 Header, Bit <0> (LSB):1
11.3
Boundary Scan Description Language (BSDL) File
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the IEEE 1149.1 test interface.
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12.0 Memory Address Mappings
Data Sheet
When the most significant bit, A14, of the address bus is set to'1', the microprocessor performs an access to one of the device's internal memories. The Control Register bits MS[2:0] indicate which memory (Local Connection, Local Data, Backplane Connection, or Backplane Data) is being accessed. Address bits A0-A13 indicate which location within the particular memory is being accessed. Address Bit A14 Description Selects memory or register access (0 = register, 1 = memory). Note that which memory (Local Connection, Local Data, Backplane Connection, Backplane Data) is accessed depends on the MS[2:0] bits in the Control Register. Stream address (0 - 15) Only streams 0 to 7 are used when the target side (Local/Backplane) is operating at 32.768 Mbps. Channel address (0 - 511) Channels 0 to 31 are used when serial stream is at 2.048 Mbps Channels 0 to 63 are used when serial stream is at 4.096 Mbps Channels 0 to 127 are used when serial stream is at 8.192 Mbps Channels 0 to 255 are used when serial stream is at 16.384 Mbps Channels 0 to 511 are used when serial stream is at 32.768 Mbps Table 11 - Address Map for Data and Connection Memory Locations (A14 = 1) The device contains two data memory blocks, one for received Backplane data and one for received Local data. For all data rates, the received data is converted to parallel format by internal serial-to-parallel converters and stored sequentially in the relevant data memory.
A13-A9
A8-A0
12.1
Local Data Memory Bit Definition
The 8-bit Local Data Memory (LDM) has 4,096 positions. The locations are associated with the Local input streams and channels. As explained in the section above, address bits A13-A0 of the microprocessor define the addresses of the streams and the channels. The LDM is read-only and configured as follows:
Bit 15:8 7:0
Name Reserved LDM Set to a default value of 8'h00.
Description
Local Data Memory - Local Input Channel Data. The LDM[7:0] bits contain the timeslot data from the Local side input TDM stream. LDM[7] corresponds to the first bit received, i.e., bit 7 in ST-BUS mode, bit 0 in GCI-Bus mode. See Figure 6, ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates for the arrival order of the bits. Table 12 - Local Data Memory (LDM) Bits
Note that the Local Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the table above are presented to provide 16-bit microprocessor read accesses.
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12.2 Backplane Data Memory Bit Definition
Data Sheet
The 8-bit Backplane Data Memory (BDM) has 4,096 positions. The locations are associated with the Backplane input streams and channels. As explained previously, address bits A13-A0 of the microprocessor define the addresses of the streams and the channels. The BDM is read-only and configured as follows: Bit 15:8 7:0 Name Reserved BDM Set to a default value of 8'h00. Backplane Data Memory - Backplane Input Channel Data. The BDM[7:0] bits contain the timeslot data from the Backplane side input TDM stream. BDM[7] corresponds to the first bit received, i.e., bit 7 in ST-BUS mode, bit 0 in GCI-Bus mode. See Figure 6, ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates for the arrival order of the bits. Table 13 - Backplane Data Memory (BDM) Bits Note that the Backplane Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the table above are presented to provide 16-bit microprocessor read accesses. Description
12.3
Local Connection Memory Bit Definition
The Local Connection Memory (LCM) has 4,096 addresses of 16-bit words. Each address, accessed through bits A13-A0 of the microprocessor port, is allocated to an individual Local output stream and channel. The bit definition for each 16-bit word is presented in Table 14 for Non-32 Mbps Source-to-Local Mode connections, and in Table 15 for 32 Mbps Source-to-Local Mode connections. The most-significant bit in the memory location, LSRC, selects the switch configuration for Backplane-to-Local or Local-to-Local. When the per-channel Message Mode is selected (LMM memory bit = HIGH), the lower byte of the LCM word (LCAB[7:0]) will be transmitted as data on the output stream (LSTo0-15) in place of data defined by the Source Control, Stream and Channel Address bits.
.
Bit 15
Name LSRC
Description Local Source Control Bit When LOW, the source is from the Backplane input port (Backplane Data Memory). When HIGH, the source is from the Local input port (Local Data Memory). Ignored when LMM is set HIGH. Local Message Mode Bit When LOW, the channel is in Connection Mode (data to be output on channel originated in Local or Backplane Data Memory). When HIGH, the channel is in Message Mode (data to be output on channel originated in Local Connection Memory). Local Output Enable Bit When LOW, the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the LORS pin. When HIGH, the channel is active. Table 14 - LCM Bits for Non-32Mbps Source-to-Local Switching
14
LMM
13
LE
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Bit 12:8 Name LSAB[4:0] Description Source Stream Address Bits The binary value of these 5 bits represents the input stream number. Ignored when LMM is set HIGH.
Data Sheet
7:0
LCAB[7:0]
Source Channel Address Bits / Message Mode Data The binary value of these 8 bits represents the input channel number when LMM is set LOW. Transmitted as data when LMM is set HIGH. Note: When LMM is set HIGH, in both ST-BUS and GCI-Bus modes, the LCAB[7:0] bits are output sequentially to the timeslot with LCAB[7] being output first.
Table 14 - LCM Bits for Non-32Mbps Source-to-Local Switching (continued)
Bit 15
Name LSRC
Description Local Source Control Bit When LOW, the source is from the Backplane input port (Backplane Data Memory). When HIGH, the source is from the Local input port (Local Data Memory). Ignored when LMM is set HIGH. Local Message Mode Bit When LOW, the channel is in Connection Mode (data to be output on channel originated in Local or Backplane Data Memory). When HIGH, the channel is in Message Mode (data to be output on channel originated in Local Connection Memory). Local Output Enable Bit When LOW, the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the LORS pin. When HIGH, the channel is active. Source Stream Address Bits The binary value of these 4 bits represents the input stream number. Ignored when LMM is set HIGH. Source Channel Address Bits / Message Mode Data The binary value of these 9 bits represents the input channel number, when LMM is LOW. Bits LCAB[7:0] transmitted as data when LMM is set HIGH. Note: When LMM is set HIGH, in both ST-BUS and GCI-Bus modes, the LCAB[7:0] bits are output sequentially to the timeslot with LCAB[7] being output first. Table 15 - LCM Bits for 32 Mbps Source-to-Local Switching
14
LMM
13
LE
12:9
LSAB[3:0]
8:0
LCAB[8:0]
12.4
Backplane Connection Memory Bit Definition
The Backplane Connection Memory (BCM) has 4,096 addresses of 16-bit words. Each address, accessed through bits A13-A0 of the microprocessor port, is allocated to an individual Backplane output stream and channel. The bit definition for each 16-bit word is presented in Table 16 for Non-32 Mbps Source-to-Backplane Mode connections, and in Table 17 for 32 Mbps Source-to-Backplane Mode connections. The most-significant bit in the memory location, BSRC, selects the switch configuration for Local-to-Backplane or Backplane-to-Backplane. When the per-channel Message Mode is selected (BMM memory bit = HIGH), the lower byte of the BCM word (BCAB[7:0]) will be transmitted as data on the output stream (BSTo0-15) in place of data defined by the Source Control, Stream and Channel Address bits.
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Bit 15 Name BSRC Description
Data Sheet
Backplane Source Control Bit When LOW, the source is from the Local input port (Local Data Memory). When HIGH, the source is from the Backplane input port (Backplane Data Memory). Ignored when BMM is set HIGH. Backplane Message Mode Bit When LOW, the channel is in Connection Mode (data to be output on channel originated in Backplane or Local Data Memory). When HIGH, the channel is in Message Mode (data to be output on channel originated in Backplane Connection Memory). Backplane Output Enable Bit When LOW, the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the BORS pin. When HIGH, the channel is active. Source Stream Address Bits The binary value of these 5 bits represents the input stream number. Ignored when BMM is set HIGH. Source Channel Address Bits / Message Mode Data The binary value of these 8 bits represents the input channel number when BMM is set LOW. Transmitted as data when BMM is set HIGH. Note: When BMM is set HIGH, in both ST-BUS and GCI-Bus modes, the BCAB[7:0] bits are output sequentially to the timeslot with BCAB[7] being output first.
14
BMM
13
BE
12:8
BSAB[4:0]
7:0
BCAB[7:0]
Table 16 - BCM Bits for Non-32Mbps Source-to-Backplane Switching
Bit 15
Name BSRC
Description Backplane Source Control Bit When LOW, the source is from the Local input port (Local Data Memory). When HIGH, the source is from the Backplane input port (Backplane Data Memory). Ignored when BMM is set HIGH. Backplane Message Mode Bit When LOW, the channel is in Connection Mode (data to be output on channel originated in Backplane or Local Data Memory). When HIGH, the channel is in Message Mode (data to be output on channel originated in Backplane Connection Memory). Backplane Output Enable Bit When LOW, the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the BORS pin. When HIGH, the channel is active. Source Stream Address Bits The binary value of these 4 bits represents the input stream number. Ignored when BMM is set HIGH. Table 17 - BCM Bits for 32 Mbps Source-to-Backplane Switching
14
BMM
13
BE
12:9
BSAB[3:0]
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Bit 8:0 Name BCAB[8:0] Description
Data Sheet
Source Channel Address Bits / Message Mode Data The binary value of these 9 bits represents the input channel number, when BMM is LOW. Bits BCAB[7:0] transmitted as data when BMM is set HIGH. Note: When BMM is set HIGH, in both ST-BUS and GCI-Bus modes, the BCAB[7:0] bits are output sequentially to the timeslot with BCAB[7] being output first.
Table 17 - BCM Bits for 32 Mbps Source-to-Backplane Switching (continued)
13.0
Internal Register Mappings
When the most significant bit, A14, of the address bus is set to'0', the microprocessor is performing an access to one of the device's internal registers. Address bits A13-A0 indicate which particular register is being accessed. A14-A0 0000H 0001H 0002H 0003H - 0012H 0023H - 0032H 0043H - 0052H 0063H - 0072H 0083H - 0092H 00A3H - 00B2H 00C3H 00C4H 00C5H 00C6H 00C7H 00C8H 00C9H 00CAH 00CBH 00CCH 00CDH - 00DCH 00EDH - 00FCH Control Register, CR Block Programming Register, BPR BER Control Register, BERCR Local Input Channel Delay Register 0 - 15, LCDR0 - 15 Local Input Bit Delay Register 0 - 15, LIDR0 - 15 Backplane Input Channel Delay Register 0 - 15, BCDR0 - 15 Backplane Input Bit Delay Register 0 - 15, BIDR0 - 15 Local Output Advancement Register 0 - 15, LOAR0 - 15 Backplane Output Advancement Register 0 - 15, BOAR0 - 15 Local BER Start Send Register, LBSSR Local Transmit BER Length Register, LTXBLR Local Receive BER Length Register, LRXBLR Local BER Start Receive Register, LBSRR Local BER Count Register, LBCR Backplane BER Start Send Register, BBSSR Backplane Transmit BER Length Register, BTXBLR Backplane Receive BER Length Register, BRXBLR Backplane BER Start Receive Register, BBSRR Backplane BER Count Register, BBCR Local Input Bit Rate Register 0 - 15, LIBRR0 - 15 Local Output Bit Rate Register 0 - 15, LOBRR0 - 15 Table 18 - Address Map for Registers (A14 = 0) Register
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A14-A0 010DH - 011CH 012DH - 013CH 014DH 3FFFH Register Backplane Input Bit Rate Register 0 - 15, BIBRR0 - 15 Backplane Output Bit Rate Register 0 - 15, BOBRR0 - 15 Memory BIST Register, MBISTR Device Identification Register, DIR Table 18 - Address Map for Registers (A14 = 0) (continued)
Data Sheet
14.0
Detailed Register Descriptions
This section describes the registers that are used in the device.
14.1
Control Register (CR)
Address 0000H. The Control Register defines which memory is to be accessed. It initiates the memory block programming mode and selects the Backplane and Local data rate modes. The Control Register (CR) is configured as follows: Reset Value 0
Bit 15:13
Name FBD_ MODE[2:0]
Description Frame Boundary Discriminator Mode When set to 111B, the Frame Boundary Discriminator can handle both low frequency and high frequency jitter. When set to 000B, the Frame Boundary Discriminator is set to handle lower frequency jitter only. All other values are reserved. These bits are ignored when FBDEN bit is LOW. Sample Point Mode When LOW the input bit sampling point is always at the 3/4 bit location. The input bit fractional delay is programmed in 1/4 bit increments from 0 to 7 3/4 as per the value of the LIDR0 to LIDR15 and BIDR0 to BIDR15 registers. When HIGH, the input bit sampling point is programmed to the 3/4, 4/4, 1/4, 2/4 bit location as per the value of the LIDR0 to LIDR15 and BIDR0 to BIDR15 registers. In addition the incoming data can be delayed by 0 to 7 bits in 1 bit increments. See Table 24, Table 25, Table 28 and Table 29 for details. Reserved Must be set to 0 for normal operation Frame Boundary Discriminator Enable When LOW, the frame boundary discriminator function is disabled. When HIGH, enables frame boundary discriminator function which allows the device to tolerate inconsistent frame boundaries, hence improving the tolerance to cycle-to-cycle variation on the input clock. Local 32MHz Mode When LOW, Local streams LSTi0-15 and LSTo0-15 can be individually programmed for data rates of 2, 4, 8, or 16 Mbps. When HIGH, Local streams LSTi0-7 and LSTo0-7 operate at 32.768 Mbps only and LSTi8-15 and LSTo8-15 are unused. Table 19 - Control Register Bits
12
SMPL_ MODE
0
11 10
Reserved FBDEN
0 0
9
MODE32L
0
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Bit 8 Name FPW Reset Value 0 Description
Data Sheet
7
MODE32B
0
6
C8IPOL
0
5
COPOL
0
4
MBP
0
3
OSB
0
Frame Pulse Width When LOW, the user must apply a 122 ns frame pulse on FP8i; the FP8o pin will output a 122 ns wide frame pulse; FP16o will output a 61ns wide frame pulse. When HIGH, the user must apply a 244ns frame pulse on FP8i; the FP8o pin will output a 244 ns wide frame pulse; FP16o will output a 122 ns wide frame pulse. Backplane 32 MHz Mode When LOW, Backplane streams BSTi0-15 and BSTo0-15 may be individually programmed for data rates of 2, 4, 8, or 16 Mbps. When HIGH, Backplane streams BSTi0-7 and BSTo0-7 operate at 32.768 Mbps only and BSTi8-15 and BSTo8-15 are unused. 8 MHz Input Clock Polarity The frame boundary is aligned to the falling or rising edge of the input clock. When LOW, the frame boundary is aligned to the clock falling edge. When HIGH, the frame boundary is aligned to the clock rising edge. Output Clock Polarity When LOW, the output clock has the same polarity as the input clock. When HIGH, the output clock is inverted. This applies to both the 8 MHz (C8o) and 16 MHz (C16o) output clocks. Memory Block Programming When LOW, the memory block programming mode is disabled. When HIGH, the connection memory block programming mode is ready to program the Local Connection Memory (LCM) and the Backplane Connection Memory (BCM). Output Stand By This bit enables the BSTo0-15 and LSTo0-15 serial outputs.
ODE Pin 0 1 1 OSB bit X 0 1 BSTo0-15, LSTo0-15 Disabled Disabled Enabled
Output Control with ODE pin and OSB bit When LOW, BSTo0-15 and LSTo0-15 are driven HIGH or high impedance, dependent on the BORS and LORS pin settings respectively, and BCSTo0-1 and LCSTo0-1 are driven low. When HIGH, BSTo0-15, LSTo0-15, BCSTo0-1 and LCSTo0-1 are enabled. Reserved Must be set to 0 for normal operation Memory Select Bits These three bits select the connection or data memory for subsequent microport memory access operations: 00 selects Local Connection Memory (LCM) for read or write operations. 01 selects Backplane Connection Memory (BCM) for read or write operations. 10 selects Local Data Memory (LDM) for read-only operation. 11 selects Backplane Data Memory (BDM) for read-only operation. Table 19 - Control Register Bits (continued)
2 1:0
Reserved MS[1:0]
0 0
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Data Sheet
Frame Boundary
(a) Frame Pulse Width = 122 ns, Control Register Bit8 (FPW) = 0 Control Register Bit6 (C8IPOL) = 0
C8i FP8i
(b) Frame Pulse Width = 122 ns, Control Register Bit8 (FPW) = 0 Control Register Bit6 (C8IPOL) = 1
C8i FP8i
(c) Frame Pulse Width = 244 ns, Control Register Bit8 (FPW) = 1 Control Register Bit6 (C8IPOL) = 0
C8i FP8i
(d) Frame Pulse Width = 244 ns, Control Register Bit8 (FPW) = 1 Control Register Bit6 (C8IPOL) = 1
C8i FP8i
Figure 22 - Frame Boundary Conditions, ST-BUS Operation
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Data Sheet
Frame Boundary
(e) Pulse Width = 122 ns, Control Register Bit8 (FPW) = 0 Control Register Bit6 (C8IPOL) = 0
C8i FP8i
(f) Pulse Width = 122 ns, Control Register Bit8 (FPW) = 0 Control Register Bit6 (C8IPOL) = 1
C8i FP8i
(g) Pulse Width = 244 ns, Control Register Bit8 (FPW) = 1 Control Register Bit6 (C8IPOL) = 0
C8i FP8i
(h) Pulse Width = 244 ns, Control Register Bit8 (FPW) = 1 Control Register Bit6 (C8IPOL) = 1
C8i FP8i
Figure 23 - Frame Boundary Conditions, GCI-Bus Operation
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14.2 Block Programming Register (BPR)
Data Sheet
Address 0001H. The Block Programming Register stores the bit patterns to be loaded into the connection memories when the Memory Block Programming feature is enabled. The BPE, LBPD[2:0] and BBPD[2:0] bits in the BPR register must be defined in the same write operation. The BPE bit is set HIGH to commence the block programming operation. Programming is completed in one frame period and may be initiated at any time within a frame. The BPE bit returns to LOW to indicate that the block programming function has completed. When BPE is HIGH, no other bits of the BPR register may be changed for at least a single frame period, except to abort the programming operation. The programming operation may be aborted by setting either BPE to LOW, or the Control Register bit, MBP, to LOW. The BPR register is configured as follows.
.
Bit 15:7 6:4
Name Reserved BBPD[2:0]
Reset Value 0 0
Description Reserved Must be set to 0 for normal operation Backplane Block Programming Data These bits refer to the value loaded into the Backplane Connection Memory (BCM) when the Memory Block Programming feature is activated. When the MBP bit in the Control Register (CR) is set HIGH and BPE (in this register) is set HIGH, the contents of bits BBPD[2:0] are loaded into bits 15-13, respectively, of the BCM. Bits 12-0 of the BCM are set LOW. Local Block Programming Data These bits refer to the value loaded into the Local Connection Memory (LCM), when the Memory Block Programming feature is activated. When the MBP bit in the Control Register is set HIGH and BPE (in this register) is set HIGH, the contents of bits LBPD[2:0] are loaded into bits 15-13, respectively, of the LCM. Bits 12-0 of the LCM are set LOW. Block Programming Enable A LOW to HIGH transition of this bit enables the Memory Block Programming function. A LOW will be returned after 125 s, upon completion of programming. Set LOW to abort the programming operation. Table 20 - Block Programming Register Bits
3:1
LBPD[2:0]
0
0
BPE
0
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14.3 Bit Error Rate Test Control Register (BERCR)
Data Sheet
Address 0002H. The BER Test Control Register controls Backplane and Local port BER testing. It independently enables and disables transmission and reception. It is configured as follows: Reset Value 0 0
Bit 15:1 2 11
Name Reserved LOCKB
Description Reserved Must be set to 0 for normal operation Backplane Lock (READ ONLY) This bit is automatically set HIGH when the receiver has locked to the incoming data sequence. The bit is reset by a LOW to HIGH transition on SBERRXB. PBER Reset for Backplane A LOW to HIGH transition initializes the Backplane BER generator to the seed value. Clear Bit Error Rate Register for Backplane A LOW to HIGH transition in this bit resets the Backplane internal bit error counter and the Backplane Bit Error Register (BBERR) to zero. Start Bit Error Rate Receiver for Backplane A LOW to HIGH transition enables the Backplane BER receiver. The receiver monitors incoming data for reception of the seed value. When detected, the LOCK state is indicated (LOCKB), the receiver compares the incoming bits with the reference generator for bit equality, and increments the Backplane Bit Error Register (BBCR) on each failure. When LOW, bit comparison is disabled and the error count is frozen. Start Bit Error Rate Transmitter for Backplane A LOW to HIGH transition starts the BER transmission on the Backplane. When LOW, Backplane transmission is disabled. BER Mode Select for Backplane When HIGH, a PRBS sequence of length 223-1 is selected for the Backplane port. When LOW, a PRBS sequence of length 215-1 is selected for the Backplane port. Local Lock (READ ONLY) This bit is automatically set HIGH when the receiver has locked to the incoming data sequence. The bit is reset by a LOW to HIGH transition on SBERRXL PBER Reset for Local A LOW to HIGH transition initializes the Local BER generator to the seed value. Clear Bit Error Rate Register for Local A LOW to HIGH transition resets the Local internal bit error counter and the Local Bit Error Register (LBERR) to zero.
10
PRSTB
0
9
CBERB
0
8
SBERRXB
0
7
SBERTXB
0
6
PRBSB
0
5
LOCKL
0
4 3
PRSTL CBERL
0 0
Table 21 - Bit Error Rate Test Control Register (BERCR) Bits
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Bit 2 Name SBERRXL Reset Value 0 Description
Data Sheet
Start Bit Error Rate Receiver for Local A LOW to HIGH transition enables the Local BER receiver. The receiver monitors incoming data for reception of the seed value. When detected, the LOCK state is indicated (LOCKL), the receiver compares the incoming bits with the reference generator for bit equality, and increments the Local Bit Error Register (LBCR) on each failure. When LOW, bit comparison is disabled and the error count is frozen. Start Bit Error Rate Transmitter for Local A LOW to HIGH transition enables the Local BER transmission. When LOW, Local transmission is disabled. BER Mode Select for Local When HIGH, a PRBS sequence of length 223-1 is selected for the Local port. When LOW, a PRBS sequence of length 215-1 is selected for the Local port.
1
SBERTXL
0
0
PRBSL
0
Table 21 - Bit Error Rate Test Control Register (BERCR) Bits (continued)
14.4
Local Input Channel Delay Registers (LCDR0 to LCDR15)
Addresses 0003h to 0012H. Sixteen Local Input Channel Delay Registers (LCDR0 to LCDR15) allow users to program the input channel delay for the Local input data streams LSTi0-15. The maximum possible adjustment is 511 channels and the LCDR0 to LCDR15 registers are configured as follows:
:
LCDRn Bit
(where n = 0 to 15 for Local Non-32 Mbps Mode, n = 0 to 7 for Local 32 Mbps Mode)
Name
Reset Value 0 0
Description
15:9 8:0
Reserved LCD[8:0]
Reserved Must be set to 0 for normal operation Local Channel Delay Register The binary value of these bits refers to the channel delay value for the Local input stream.
Table 22 - Local Input Channel Delay Register (LCDRn) Bits
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14.4.1 Local Channel Delay Bits 8-0 (LCD8 - LCD0)
Data Sheet
These nine bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data from the Local input pins. The input channel delay can be selected to be up to 511 (32 Mbps streams), 255 (16 Mbps streams), 127 (8 Mbps streams), 63 (4 Mbps streams) or 31 (2 Mbps streams) channels from the frame boundary. Input Stream Channel Delay 0 Channel (Default) 1 Channel 2 Channels 3 Channels 4 Channels 5 Channels ... 509 Channels 510 Channels 511 Channels Corresponding Delay Bits LCD8-LCD0 0 0000 0000 0 0000 0001 0 0000 0010 0 0000 0011 0 0000 0100 0 0000 0101 ... 1 1111 1101 1 1111 1110 1 1111 1111
Table 23 - Local Input Channel Delay (LCD) Programming Table
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14.5 Local Input Bit Delay Registers (LIDR0 to LIDR15)
Addresses 0023H to 0032H. There are sixteen Local Input Delay Registers (LIDR0 to LIDR15).
Data Sheet
When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit location and LIDR0 to LIDR15 define the input bit and fractional bit delay of each Local stream. The possible bit delay adjustment is up to 73/4 bits, in steps of 1/4 bit. When the SMPL_MODE bit is HIGH, LIDR0 to LIDR15 define the input bit sampling point as well as the integer bit delay of each Local stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay can be adjusted in 1-bit increments from 0 to 7 bits. The LIDR0 to LIDR15 registers are configured as follows: LIDRn Bit
(where n = 0 to 15 for Local Non-32 Mbps Mode, n = 0 to 7 for Local 32 Mbps Mode)
Name
Reset Value 0 0
Description
15:5 4:0
Reserved LID[4:0]
Reserved Must be set to 0 for normal operation Local Input Bit Delay Register When SMPL_MODE = LOW, the binary value of these bits refers to the input bit and fractional bit delay value (0 to 73/4). When SMPL_MODE = HIGH, the binary value of LID[1:0] refers to the input bit sampling point (1/4 to 4/4). LID[4:2] refers to the integer bit delay value (0 to 7 bits).
Table 24 - Local Input Bit Delay Register (LIDRn) Bits
14.5.1
Local Input Delay Bits 4-0 (LID[4:0])
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to sample each input. Input bit delay adjustment can range up to 73/4 bit periods forward, with resolution of 1/4 bit period. The default sampling point is at the 3/4 bit location. This can be described as: no. of bits delay = LID[4:0] / 4 For example, if LID[4:0] is set to 10011 (19), the input bit delay = 19 * 1/4 = 43/4. When SMPL_MODE = HIGH, the binary value of LID[1:0] refers to the input bit sampling point (1/4 to 4/4). LID[4:2] refers to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7 and that the sampling point can vary from 1/4 to 4/4 in 1/4 bit increments. Table 25 illustrates the bit delay and sampling point selection. LIDn LID4 0 0 LID3 0 0 LID2 0 0 LID1 0 0 LID0 0 1 SMPL_MODE = LOW Input Data Bit Delay 0 (Default) 1/4 SMPL_MODE = HIGH Input Data Bit Delay 0 (Default) 0 Input Data Sampling Point 3/4 4/4
Table 25 - Local Input Bit Delay and Sampling Point Programming Table 61
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LIDn LID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LID3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LID2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SMPL_MODE = LOW Input Data Bit Delay 1/2 3/4 1 1 1/4 1 1/2 1 3/4 2 2 1/4 2 1/2 2 3/4 3 3 1/4 3 1/2 3 3/4 4 4 1/4 4 1/2 4 3/4 5 5 1/4 5 1/2 5 3/4 6 6 1/4 6 1/2 6 3/4 7 7 1/4 7 1/2 7 3/4 SMPL_MODE = HIGH Input Data Bit Delay 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7
Data Sheet
Input Data Sampling Point 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4
Table 25 - Local Input Bit Delay and Sampling Point Programming Table (continued)
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14.6 Backplane Input Channel Delay Registers (BCDR0 to BCDR15)
Data Sheet
Addresses 0043H to 0052H Sixteen Backplane Input Channel Delay Registers (BCDR0 to BCDR15) allow users to program the input channel delay for the Backplane input data streams BSTi0-15. The maximum possible adjustment is 511 channels and the BCDR0 to BCDR15 registers are configured as follows: BCDRn Bit
(where n = 0 to 15 for Backplane Non-32 Mbps Mode, n = 0 to 7 for Backplane 32 Mbps Mode)
Name
Reset Value
Description
15:9 8:0
Reserved BCD[8:0]
0 0
Reserved Must be set to 0 for normal operation Backplane Channel Delay Register The binary value of these bits refers to the channel delay value for the Backplane input stream.
Table 26 - Backplane Input Channel Delay Register (BCDRn) Bits
14.6.1
Backplane Channel Delay Bits 8-0 (BCD8 - BCD0)
These nine bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data from the Backplane input pins. The input channel delay can be selected to be up to 511 (32 Mbps streams), 255 (16 Mbps streams), 127 (8 Mbps streams), 63 (4 Mbps streams) or 31 (2 Mbps streams) channels from the frame boundary.
Input Stream Channel Delay 0 Channel (Default) 1 Channel 2 Channels 3 Channels 4 Channels 5 Channels ... 509 Channels 510 Channels 511 Channels
Corresponding Delay Bits BCD8-BCD0 0 0000 0000 0 0000 0001 0 0000 0010 0 0000 0011 0 0000 0100 0 0000 0101 ... 1 1111 1101 1 1111 1110 1 1111 1111
Table 27 - Backplane Input Channel Delay (BCD) Programming Table
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14.7 Backplane Input Bit Delay Registers (BIDR0 to BIDR15)
Data Sheet
Addresses 0063H to 0072H There are sixteen Backplane Input Delay Registers (BIDR0 to BIDR15). When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit location and BIDR0 to BIDR15 define the input bit and fractional bit delay of each Backplane stream. The possible bit delay adjustment is up to 73/4 bits, in steps of 1/4 bit. When the SMPL_MODE bit is HIGH, BIDR0 to BIDR15 define the input bit sampling point as well as the integer bit delay of each Backplane stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay can be adjusted in 1-bit increments from 0 to 7 bits. The BIDR0 to BIDR15 registers are configured as follows: BIDRn Bit
(where n = 0 to 15 for Backplane Non-32 Mbps Mode, n = 0 to 7 for Backplane 32 Mbps Mode)
Name
Reset Value
Description
15:5 4:0
Reserved BID[4:0]
0 0
Reserved Must be set to 0 for normal operation Backplane Input Bit Delay Register When SMPL_MODE = LOW, the binary value of these bits refers to the input bit fractional delay value (0 to 73/4). When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point (1/4 to 4/4). BID[4:2] refers to the integer bit delay value (0 to 7 bits).
Table 28 - Backplane Input Bit Delay Register (BIDRn) Bits
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14.7.1 Backplane Input Delay Bits 4-0 (BID[4:0])
Data Sheet
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to sample each input. Input bit delay adjustment can range up to 73/4 bit periods forward, with resolution of 1/4 bit period. The default sampling point is at the 3/4 bit location. This can be described as: no. of bits delay = BID[4:0] / 4 For example, if BID[4:0] is set to 10011 (19), the input bit delay = 19 * 1/4 = 43/4. When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point (1/4 to 4/4). BID[4:2] refers to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7 and that the sampling point can vary from 1/4 to 4/4 in 1/4 bit increments. Table 29 illustrates the bit delay and sampling point selection. BIDn BID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 BID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 BID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 BID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 BID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 SMPL_MODE = LOW Input Data Bit Delay 0 (Default) 1/4 1/2 3/4 1 1 1/4 1 1/2 1 3/4 2 2 1/4 2 1/2 2 3/4 3 3 1/4 3 1/2 3 3/4 4 4 1/4 4 1/2 4 3/4 5 5 1/4 5 1/2 5 3/4 6 6 1/4 6 1/2 SMPL_MODE = HIGH Input Data Bit Delay 0 (Default) 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 Input Data Sampling Point 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4
Table 29 - Backplane Input Bit Delay and Sampling Point Programming Table
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BIDn BID4 1 1 1 1 1 BID3 1 1 1 1 1 BID2 0 1 1 1 1 BID1 1 0 0 1 1 BID0 1 0 1 0 1 SMPL_MODE = LOW Input Data Bit Delay 6 3/4 7 7 1/4 7 1/2 7 3/4 SMPL_MODE = HIGH Input Data Bit Delay 6 7 7 7 7
Data Sheet
Input Data Sampling Point 2/4 3/4 4/4 1/4 2/4
Table 29 - Backplane Input Bit Delay and Sampling Point Programming Table (continued)
14.8
Local Output Advancement Registers (LOAR0 to LOAR15)
Addresses 0083H to 0092H. Sixteen Local Output Advancement Registers (LOAR0 to LOAR15) allow users to program the output advancement for output data streams LSTo0 to LSTo15. For 2 Mbps, 4 Mbps, 8 Mbps and 16 Mbps stream operation, the possible adjustment is -2 (15 ns), -4 (31 ns) or -6 (46 ns) cycles of the internal system clock (131.072 MHz). For 32 Mbps stream operation, the possible adjustment is -1 (7.6 ns), -2 (15 ns) or -3 (23 ns) cycles of the internal system clock (131.072 MHz). The LOAR0 to LOAR15 registers are configured as follows: LOARn Bit
(where n = 0 to 15 for Local Non-32 Mbps Mode, n = 0 to 7 for Local 32 Mbps Mode)
Name
Reset Value 0 0
Description
15:2 1:0
Reserved LOA[1:0]
Reserved Must be set to 0 for normal operation Local Output Advancement Value
Table 30 - Local Output Advancement Register (LOAR) Bits
14.8.1
Local Output Advancement Bits 1-0 (LOA1-LOA0)
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal alignment with the generated frame pulse FP8o. Local Output Advancement For 2 Mbps, 4 Mbps, 8 Mbps & 16 Mbps Clock Rate 131.072 MHz 0 (Default) -2 cycles (~15 ns) Local Output Advancement For 32 Mbps Clock Rate 131.072 MHz 0 (Default) -1 cycle (~7.6 ns) Corresponding Advancement Bits LOA1 0 0 LOA0 0 1
Table 31 - Local Output Advancement (LOAR) Programming Table
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Local Output Advancement For 2 Mbps, 4 Mbps, 8 Mbps & 16 Mbps Clock Rate 131.072 MHz -4 cycles (~31 ns) -6 cycles (~46 ns) Local Output Advancement For 32 Mbps Clock Rate 131.072 MHz -2 cycles (~15 ns) -3 cycles (~23 ns)
Data Sheet
Corresponding Advancement Bits LOA1 1 1 LOA0 0 1
Table 31 - Local Output Advancement (LOAR) Programming Table (continued)
14.9
Backplane Output Advancement Registers (BOAR0 - BOAR15)
Addresses 00A3H to 00B2H Sixteen Backplane Output Advancement Registers (BOAR0 to BOAR15) allow users to program the output advancement for output data streams BSTo0 to BSTo15. For 2 Mbps, 4 Mbps, 8 Mbps and 16 Mbps stream operation, the possible adjustment is -2 (15 ns), -4 (31 ns) or -6 (46 ns) cycles of the internal system clock (131.072 MHz). For 32 Mbps stream operation, the possible adjustment is -1 (7.6 ns), -2 (15 ns) or -3 (23 ns) cycles of the internal system clock (131.072 MHz). The BOAR0 to BOAR15 registers are configured as follows: BOARn Bit
(where n = 0 to 15 for Backplane Non-32 Mbps Mode, n = 0 to 7 for Backplane 32 Mbps Mode)
Name
Reset Value 0 0
Description
15:2 1:0
Reserved BOA[1:0]
Reserved Must be set to 0 for normal operation Backplane Output Advancement Value
Table 32 - Backplane Output Advancement Register (BOAR) Bits
14.9.1
Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal alignment with the generated frame pulse FP8o. Backplane Output Advancement For 2 Mbps, 4 Mbps, 8 Mbps & 16 Mbps Clock Rate 131.072 MHz 0 (Default) -2 cycles (~15 ns) -4 cycles (~31 ns) -6 cycles (~46ns) Backplane Output Advancement For 32 Mbps Clock Rate 131.072 MHz 0 (Default) -1 cycle (~7.6 ns) -2 cycles (~15 ns) -3 cycles (~23 ns) Corresponding Advancement Bits BOA1 0 0 1 1 BOA0 0 1 0 1
Table 33 - Backplane Output Advancement (BOAR) Programming Table
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14.10 14.10.1 Local Bit Error Rate (BER) Registers Local BER Start Send Register (LBSSR)
Data Sheet
Address 00C3H. The Local BER Start Send Register defines the output channel and the stream on which the BER sequence starts to be transmitted. The LBSSR register is configured differently for Non-32 Mbps and 32 Mbps Modes: Reset Value 0 0
Bit 15:13 12:8
Name Reserved LBSSA[4:0]
Description Reserved Must be set to 0 for normal operation Local BER Send Stream Address Bits The binary value of these bits refers to the Local output stream which carries the BER data. Local BER Send Channel Address Bits The binary value of these bits refers to the Local output channel at which the BER data starts to be sent.
7:0
LBSCA[7:0]
0
Table 34 - Local BER Start Send Register (LBSSR) Bits in Non-32 Mbps Mode
Bit 15:13 12:9
Name Reserved LBSSA[3:0]
Reset Value 0 0
Description Reserved Must be set to 0 for normal operation Local BER Send Stream Address Bits The binary value of these bits refers to the Local output stream which carries the BER data. Local BER Send Channel Address Bits The binary value of these bits refers to the Local output channel at which the BER data starts to be sent.
8:0
LBSCA[8:0]
0
Table 35 - Local BER Start Send Register (LBSSR) Bits in 32 Mbps Mode
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14.10.2 Local Transmit BER Length Register (LTXBLR)
Data Sheet
Address 00C4H. Local BER Transmit Length Register (LTXBLR) defines how many channels of the BER sequence will be transmitted during each frame. The minimum length of the BER transmitter is 1 channel. To set a desired BER length, set LTXBL8-0 bits for the desired length - 1 channel. For example, to run a BER test for 32 consecutive channels, program LTXBL to 000011111B. The LTXBLR register is configured as follows: Reset Value 0 0
Bit 15:9 8:0
Name Reserved LTXBL[8:0]
Description Reserved Must be set to 0 for normal operation Local Transmit BER Length Bits The binary value of these bits defines the number of channels in addition to the Start Channel allocated for the BER Transmitter. (i.e., Total Channels = LTXBL value + 1)
Table 36 - Local BER Length Register (LTXBLR) Bits
14.10.3
Local Receive BER Length Register (LRXBLR)
Address 00C5H. Local BER Receive Length Register (LRXBLR) defines how many channels of the BER sequence will be received during each frame. The minimum length of the BER receiver is 1 channel. To set a desired BER length, set LRXBL8-0 bits for the desired length - 1 channel. For example, to receive a BER test for 32 consecutive channels, program LRXBL to 000011111B. The LRXBLR register is configured as follows: Reset Value 30 60
Bit 115:9 48:0
Name 2Reserved 5LRXBL[8:0]
Description Reserved Must be set to 0 for normal operation Local Receive BER Length Bits The binary value of these bits defines the number of channels in addition to the Start Channel allocated for the BER Receiver. (i.e., Total Channels = LRXBL value + 1)
Table 37 - Local Receive BER Length Register (LRXBLR) Bits
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14.10.4 Local BER Start Receive Register (LBSRR)
Data Sheet
Address 00C6H. Local BER Start Receive Register defines the input stream and start channel at which the BER sequence shall start to be received. The LBSRR register is configured differently for Non-32 Mbps and 32 Mbps Modes: Reset Value 0 0
Bit 15:13 12:8
Name Reserved LBRSA[4:0]
Description Reserved Must be set to 0 for normal operation Local BER Receive Stream Address Bits The binary value of these bits refers to the Local input stream configured to receive the BER data. Local BER Receive Channel Address Bits The binary value of these bits refers to the Local input channel at which the BER data starts to be compared.
7:0
LBRCA[7:0]
0
Table 38 - Local BER Start Receive Register (LBSRR) Bits for Non-32 Mbps Mode
Bit 15:13 12:9
Name Reserved LBRSA[3:0]
Reset Value 0 0
Description Reserved Must be set to 0 for normal operation Local BER Receive Stream Address Bits The binary value of these bits refers to the Local input stream configured to receive the BER data. Local BER Receive Channel Address Bits The binary value of these bits refers to the Local input channel at which the BER data starts to be compared.
8:0
LBRCA[8:0]
0
Table 39 - Local BER Start Receive Register (LBSRR) Bits for 32 Mbps Mode
14.10.5
Local BER Count Register (LBCR)
Address 00C7H. Local BER Count Register contains the number of counted errors. This register is read-only. The LBCR register is configured as follows: Reset Value 0
Local Bit Error Rate Count
Bit 15:0
Name LBC[15:0]
Description
The binary value of the bits defines the Local Bit Error count. If the number of errors exceeds the maximum counter value, this counter will stay at FFFFH until the CBERL bit in the BERCR register clears it.
Table 40 - Local BER Count Register (LBCR) Bits
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14.11 14.11.1 Backplane Bit Error Rate (BER) Registers Backplane BER Start Send Register (BBSSR)
Data Sheet
Address 00C8H. Backplane BER Start Send Register defines the output channel and the stream on which the BER sequence is transmitted. The minimum length of the BER transmitter is 1 channel. To set a desired BER length, set BTXBL8-0 bits for the desired length - 1 channel. For example, to run a BER test for 32 consecutive channels, program BTXBL to 000011111B. The BBSSR register is configured as follows: Reset Value 0 0
Bit 15:14 13:9
Name Reserved BBSSA[4:0]
Description Reserved Must be set to 0 for normal operation Backplane BER Send Stream Address Bits The binary value of these bits refers to the Backplane output stream which carries the BER data. Backplane BER Send Channel Address Bits The binary value of these bits refers to the Backplane output channel at which the BER data starts to be sent.
8:0
BBSCA[8:0]
0
Table 41 - Backplane BER Start Send Register (BBSSR) Bits
14.11.2
Backplane Transmit BER Length Register (BTXBLR)
Address 00C9H. Backplane Transmit BER Length Register (BTXBLR) defines how many channels of the BER sequence will be transmitted in each frame. The minimum length of the BER receiver is 1 channel. To set a desired BER length, set BRXBL8-0 bits for the desired length - 1 channel. For example, to receive a BER test for 32 consecutive channels, program BRXBL to 000011111B. The BTXBLR register is configured as follows: Reset Value 0 0
Bit 15:9 8:0
Name Reserved BTXBL[8:0]
Description Reserved Must be set to 0 for normal operation Backplane Transmit BER Length Bits The binary value of these bits defines the number of channels in addition to the Start Channel allocated for the BER Transmitter. (i.e., Total Channels = BTXBL value + 1)
Table 42 - Backplane Transmit BER Length (BTXBLR) Bits
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14.11.3 Backplane Receive BER Length Register (BRXBLR)
Data Sheet
Address 00CAH. Backplane Receive BER Length Register (BRXBLR) defines how many channels of the BER sequence will be received in each frame. The BRXBLR register is configured as follows: Reset Value 0 0
Bit 15:9 8:0
Name Reserved BRXBL[8:0]
Description Reserved Must be set to 0 for normal operation Backplane Receive BER Length Bits The binary value of these bits defines the number of channels in addition to the Start Channel allocated for the BER Receiver. (i.e., Total Channels = BRXBL value + 1)
Table 43 - Backplane Receive BER Length (BRXBLR) Bits
14.11.4
Backplane BER Start Receive Register (BBSRR)
Address 00CBH. Backplane BER Start Receive Register defines the input stream and the start channel at which the BER sequence shall start to be received. The BBSRR register is configured as follows: Reset Value 0 0
Bit 15:14 13:9
Name Reserved BBRSA[4:0]
Description Reserved Must be set to 0 for normal operation Backplane BER Receive Stream Address Bits The binary value of these bits refers to the Backplane input stream configured to receive the BER data. Backplane BER Receive Channel Address Bits The binary value of these bits refers to the Backplane input channel at which the BER data starts to be compared.
8:0
BBRCA[8:0]
0
Table 44 - Backplane BER Start Receive Register (BBSRR) Bits
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14.11.5 Backplane BER Count Register (BBCR)
Data Sheet
Address 00CCH. Backplane BER Count Register contains the number of counted errors. This register is read-only. The BBCR register is configured as follows: Reset Value 0
Bit 15:0
Name BBC[15:0]
Description Backplane Bit Error Rate Count The binary value of these bits defines the Backplane Bit Error count. If the number of errors exceeds the maximum counter value, this counter will stay at FFFFH until the CBERB bit in the BERCR register clears it.
Table 45 - Backplane BER Count Register (BBCR) Bits
14.12 14.12.1
Local Bit Rate Registers Local Input Bit Rate Registers (LIBRR0 - LIBRR15)
Addresses 00CDH to 00DCH. Sixteen Local Input Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or 16 Mbps. These registers may be overridden by setting Local 32 Mbps Mode in the Control Register (via the MODE32L bit), in which case, Local input streams 0-7 will operate at 32 Mbps and Local input streams 8-15 will be unused. The LIBRR registers are configured as follows: LIBRn
(for n=0 to 15)
Name Reserved LIBR[1:0]
Reset Value 0 0
Description Reserved Must be set to 0 for normal operation Local Input Bit Rate
15:2 1:0
Table 46 - Local Input Bit Rate Register (LIBRR) Bits
MODE32L 0 0 0 0 1
LIBR1 0 0 1 1 X
LIBR0 0 1 0 1 X
Bit rate for stream n 2 Mbps 4 Mbps 8 Mbps 16 Mbps 32 Mbps
Table 47 - Local Input Bit Rate (LIBR) Programming Table
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14.12.2 Local Output Bit Rate Registers (LOBRR0 - LOBRR15)
Data Sheet
Addresses 00EDH to 00FCH. Sixteen Local Output Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or 16 Mbps. These registers may be overridden by setting Local 32 Mbps Mode in the Control Register (via the MODE32L bit), in which case, Local output streams 0-7 will operate at 32 Mbps and Local output streams 8-15 will be unused. The LOBRR registers are configured as follows: LOBRn Bit
(where n = 0 to 15)
Name Reserved LOBR[1:0]
Reset Value 0 0
Description Reserved Must be set to 0 for normal operation Local Output Bit Rate
15:2 1:0
Table 48 - Local Output Bit Rate Register (LOBRR) Bits
MODE32L 0 0 0 0 1
LOBR1 0 0 1 1 X
LOBR0 0 1 0 1 X
Bit rate for stream n 2 Mbps 4 Mbps 8 Mbps 16 Mbps 32 Mbps
Table 49 - Local Output Bit Rate (LOBR) Programming Table
14.13 14.13.1
Backplane Bit Rate Registers Backplane Input Bit Rate Registers (BIBRR0 - BIBRR15)
Addresses 010DH to 011CH. Sixteen Backplane Input Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or 16 Mbps. These registers may be overridden by setting Backplane 32 Mbps Mode in the Control Register (via the MODE32B bit), in which case, Backplane input streams 0-7 will operate at 32 Mbps and Backplane input streams 8-15 will be unused. The BIBRR registers are configured as follows: BIBRn Bit
(for n = 0 to 15)
Name Reserved BIBR[1:0]
Reset Value 0 0
Description Reserved Must be set to 0 for normal operation Backplane Input Bit Rate
15:2 1:0
Table 50 - Backplane Input Bit Rate Register (BIBRR) Bits
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MODE32B 0 0 0 0 1 BIBR1 0 0 1 1 X BIBR0 0 1 0 1 X Bit rate for stream n 2 Mbps 4 Mbps 8 Mbps 16 Mbps 32 Mbps
Data Sheet
Table 51 - Backplane Input Bit Rate (BIBR) Programming Table
14.13.2
Backplane Output Bit Rate Registers (BOBRR0 - BOBRR15)
Addresses 012DH to 013CH. Sixteen Backplane Output Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or 16 Mbps. These registers may be overridden by setting Backplane 32 Mbps Mode in the Control Register (via the MODE32B bit), in which case, Backplane output streams 0-7 will operate at 32 Mbps and Backplane output streams 8-15 will be unused. The BOBRR registers are configured as follows: Reset Value 0 0
BOBRn Bit
(for n = 0 to 15)
Name Reserved BOBR[1:0]
Description Reserved Must be set to 0 for normal operation Backplane Output Bit Rate
15:2 1:0
Table 52 - Backplane Output Bit Rate Register (BOBRR) Bits
MODE32B 0 0 0 0 1
BOBR1 0 0 1 1 X
BOBR0 0 1 0 1 X
Bit rate for stream n 2 Mbps 4 Mbps 8 Mbps 16 Mbps 32 Mbps
Table 53 - Backplane Output Bit Rate (BOBRR) Programming Table
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14.14 Memory BIST Register
Data Sheet
Address 014DH. The Memory BIST Register enables the self-test of chip memory. Two consecutive write operations are required to start MBIST: the first with only bit 12 (LV_TM) set HIGH (i.e., 1000h); the second with bit 12 maintained HIGH but with the required start bit(s) also set HIGH. The MBISTR register is configured as follows: Reset Value 0 0
Bit 15:13 12
Name Reserved LV_TM
Description Reserved Must be set to 0 for normal operation MBIST Test Enable Set HIGH to enable MBIST mode. Set LOW for normal operation. Backplane Data Memory Start BIST Sequence Sequence enabled on LOW to HIGH transition. Backplane Data Memory BIST Sequence Completed (Read-only) This bit must be polled - when HIGH, indicates completion of Backplane Data Memory BIST sequence. Backplane Data Memory Pass/Fail Bit (Read-only) This bit indicates the Pass/Fail status following completion of the Backplane Data Memory BIST sequence (indicated by assertion of BISTCDB). A HIGH indicates Pass, a LOW indicates Fail. Local Data Memory Start BIST Sequence Sequence enabled on LOW to HIGH transition. Local Data Memory BIST Sequence Completed (Read-only) This bit must be polled - when HIGH, indicates completion of Local Data Memory BIST sequence. Local Data Memory Pass/Fail Bit (Read-only) This bit indicates the Pass/Fail status following completion of the Local Data Memory BIST sequence (indicated by assertion of BISTCDL). A HIGH indicates Pass, a LOW indicates Fail. Backplane Connection Memory Start BIST Sequence Sequence enabled on LOW to HIGH transition. Backplane Connection Memory BIST Sequence Completed (Read-only) This bit must be polled - when HIGH, indicates completion of Backplane Connection Memory BIST sequence. Backplane Connection Memory Pass/Fail Bit (Read-only) This bit indicates the Pass/Fail status following completion of the Backplane Connection Memory BIST sequence (indicated by assertion of BISTCCB). A HIGH indicates Pass, a LOW indicates Fail. Table 54 - Memory BIST Register (MBISTR) Bits
11 10
BISTSDB BISTCDB
0 0
9
BISTPDB
0
8 7
BISTSDL BISTCDL
0 0
6
BISTPDL
0
5 4
BISTSCB BISTCCB
0 0
3
BISTPCB
0
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Bit 2 1 Name BISTSCL BISTCCL Reset Value 0 0 Description Local Connection Memory Start BIST Sequence Sequence enabled on LOW to HIGH transition.
Data Sheet
Local Connection Memory BIST Sequence Completed (Read-only) This bit must be polled - when HIGH, indicates completion of Local Connection Memory BIST sequence. Local Connection Memory Pass/Fail Bit (Read-only) This bit indicates the Pass/Fail status following completion of the Local Connection Memory BIST sequence (indicated by assertion of BISTCCL). A HIGH indicates Pass, a LOW indicates Fail.
0
BISTPCL
0
Table 54 - Memory BIST Register (MBISTR) Bits (continued)
14.15
Device Identification Register
Address 3FFFH. The Device Identification Register stores the binary value of the silicon revision number and the Device ID. This register is read-only. The DIR register is configured as follows: Bit 15:8 7:4 3 2:0 Name Reserved RC[3:0] Reserved DID[2:0] Reset Value 0 0000 0 010 Description Reserved Will be set to 0 in normal operation Revision Control Bits Reserved Will be set to 0 in normal operation Device ID
Table 55 - Device Identification Register (DIR) Bits
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15.0 DC Electrical Characteristics
Data Sheet
Absolute Maximum Ratings* Parameter 1 2 3 4 5 6 7 Core Supply Voltage I/O Supply Voltage PLL Supply Voltage Input Voltage (non-5 V tolerant inputs) Input Voltage (5 V tolerant inputs) Continuous Current at digital outputs Package power dissipation Symbol VDD_CORE VDD_IO VDD_PLL VI VI_5V Io PD Min. -0.5 -0.5 -0.5 -0.5 -0.5 Max. 2.5 5.0 2.5 VDD_IO +0.5 7.0 15 1.5 +125 Units V V V V V mA W C
- 55 8 Storage temperature TS * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions Characteristics 1 2 3 4 5 6 Operating Temperature Positive Supply Positive Supply Positive Supply Input Voltage Input Voltage on 5 V Tolerant Inputs Sym. TOP VDD_IO VDD_CORE VDD_PLL VI VI_5V Min. -40 3.0 1.71 1.71 0 0 Typ. 25 3.3 1.8 1.8 Max. +85 3.6 1.89 1.89 VDD_IO 5.5 Units C V V V V V
Voltages are with respect to ground (VSS) unless otherwise stated.
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DC Electrical Parameters Characteristics 1a 1b 1c 1d I N P U T 2 3 4 S Input High Voltage Input Low Voltage Input Leakage (input pins) Input Leakage (bi-directional pins) Weak Pullup Current 5 6 7 8 9 O U T P U T S Weak Pulldown Current Input Pin Capacitance Output High Voltage Output Low Voltage High-Impedance Leakage VIH VIL IIL IBL IPU IPD CI VOH VOL IOZ 2.4 0.4 5 2.0 0.8 5 5 200 200 5 V V A A A A pF V V A pF Supply Current Supply Current Supply Current Supply Current Sym. IDD_Core IDD_Core IDD_IO IDD_IO 14 240 Min. Typ. Max. 4 290 100 18 Units mA mA A mA
Data Sheet
Test Conditions Static IDD_Core and PLL current Applied clock C8i = 8.192 MHz Static IDD_IO IAV with all output streams at max. data rate unloaded
0 < V < VDD_IO Note 1 Input at 0V Input at VDD_IO IOH = 8mA IOL = 8mA 0 < V0 < VDD_IO Note 1
5 10 Output Pin Capacitance CO Voltages are with respect to ground (Vss) unless otherwise stated. Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V)
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16.0 AC Electrical Characteristics
Data Sheet
AC Electrical Characteristics Timing Parameter Measurement: Voltage Levels Characteristics 1 2 3 CMOS Threshold Rise/Fall Threshold Voltage High Rise/Fall Threshold Voltage Low Sym. VCT VHM VLM Level 0.5VDD_IO 0.7VDD_IO 0.3VDD_IO Units V V V Conditions 3.0V < VDD_IO < 3.6V 3.0V < VDD_IO < 3.6V 3.0V < VDD_IO < 3.6V
Input and Output Clock Timing Characteristic 1 2 3 4 5 6 7 8 FP8i, Input Frame Pulse Width Input Frame Pulse Setup Time (before C8i clock falling/rising edge) Input Frame Pulse Hold Time (from C8i clock falling/rising edge) C8i Clock Period (Average value, does not consider the effects of jitter) C8i Clock Pulse Width High C8i Clock Pulse Width Low C8i Clock Rise/Fall Time C8i Cycle to Cycle Variation (This values is with respect to the typical C8i Clock Period, and using mid-bit sampling) Output Frame Boundary Offset FP8o Frame Pulse Width Sym. tIFPW244 tIFPW122 tIFPS244 tIfPS122 tIFPH244 tIFPH122 tICP tICH tICL trIC, tfIC tCCVIC Min. 210 10 5 5 0 0 120 50 50 0 -7.0 -8.5 tOFBOS tOFPW8_244 tOFPW8_122 tFPFBF8_244 tFPFBF8_122 tFBFPF8_244 tFBFPF8_122 224 117 117 58 117 58 7 244 122 122 61 122 61 122 61 61 2 Typ. 244 122 Max. 350 220 110 60 110 60 124 70 70 3 7.0 8.5 9.5 264 127 127 64 127 64 Units ns ns ns ns ns ns ns ns ns ns ns FPW =1 FPW=0 CL=60pF FPW =1 FPW=0 CL=60pF FPW =1 FPW=0 CL=60pF 32 Mbps 16 Mbps or lower. Notes
9 10
11
FP8o Output Delay (from frame pulse edge to output frame boundary) FP8o Output Delay (from output frame boundary to frame pulse edge)
ns
12
ns
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Zarlink Semiconductor Inc.
ZL50050
Input and Output Clock Timing (continued) Characteristic 13 14 15 16 17 C8o Clock Period C8o Clock Pulse Width High C8o Clock Pulse Width Low C8o Clock Rise/Fall Time FP16o Frame Pulse Width Sym. tOCP8 tOCH8 tOCL8 trOC8, tfOC8 tOFPW16_122 tOFPW16_61 tFPFBF16_12
2
Data Sheet
Min. 117 58 58 3 117 58 58 29 58 29 58 29 29 3
Typ. 122 61 61
Max. 127 64 64 7
Units ns ns ns ns ns
Notes CL=60pF
122 61 61 31 61 31 61 31 31
127 64 64 33 64 33 64 33 33 7
FPW =1 FPW=0 CL=60pF FPW =1 FPW=0
18
FP16o Output Delay (from frame pulse edge to output frame boundary) FP16o Output Delay (from output frame boundary to frame pulse edge) C16o Clock Period C16o Clock Pulse Width High C16o Clock Pulse Width Low C16o Clock Rise/Fall Time
ns
tFPFBF16_61 tFBFPF16_12
2
19
ns
FPW =1 FPW=0
tFBFPF16_61 tOCP16 tOCH16 tOCL16 trOC16, tfOC16 ns ns ns ns CL=60pF
20 21 22 23
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Zarlink Semiconductor Inc.
ZL50050
Data Sheet
FP8i (244 ns) tIFPS244
tIFPW244
tIFPH244 tIFPW122
FP8i (122 ns) tIFPS122 tICL tICH
tIFPH122 tICP trIC
C8i
tfIC
CK_int * tOFBOS FP8o (244 ns) tFPFBF8_244
tOFPW8_122
tOFPW8_244
tFBFPF8_244
FP8o (122 ns) tFPFBF8_122 C8o tOCL8 tOCH8 tFBFPF8_122 tOCP8 trOC8 tOFPW16_122 FP16o (122 ns) tFPFBF16_122 tOFPW16_61 FP16o (61ns) tFPFB16_61 tOCL16 C16o trOC16 tfOC16 tOCH16 tFBFP16_61 tOCP16 tFBFPF16_122
tfOC8
Note *: CK_int is the internal clock signal of 131.072 MHz Note **: Although the figures above show the frame boundary as measured from the falling edge of C8i/C8o/C16o, the frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the Control Register.
Figure 24 - Input and Output Clock Timing Diagram for ST-BUS
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Zarlink Semiconductor Inc.
ZL50050
Data Sheet
FP8i (244 ns) tIFPS244 FP8i (122 ns) tIFPS122 tICL tICH tIFPW122
tIFPW244
tIFPH244
tIFPH122 tICP trIC
C8i
tfIC
CK_int * tOFBOS FP8o (244 ns) tFPFBF8_244
tOFPW8_122
tOFPW8_244
tFBFPF8_244
FP8o (122 ns) tFPFBF8_122 C8o tOCL8 tOCH8 tFBFPF8_122 tOCP8
trOC8 tOFPW16_122 FP16o (122 ns) tFPFBF16_122 tOFPW16_61 FP16o (61 ns) tFPFB16_61 tOCH16 C16o tfOC16 tOCL16 tFBFP16_61 tOCP16 tFBFPF16_122
tfOC8
trOC16
Note *: CK_int is the internal clock signal of 131.072 MHz Note **: Although the figures above show the frame boundary as measured from the rising edge of C8i/C8o/C16o, the frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the Control Register.
Figure 25 - Input and Output Clock Timing Diagram for GCI-Bus
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Zarlink Semiconductor Inc.
ZL50050
Local and Backplane Data Timing Characteristic 1 Local/Backplane Input Data Sampling Point Sym. tIDS32 tIDS16 tIDS8 tIDS4 tIDS2 tSIS32 tSIS16 tSIS8 tSIS4 tSIS2 tSIH32 tSIH16 tSIH8 tSIH4 tSIH2 tOFBOS tSOD32 tSOD16 tSOD8 tSOD4 tSOD2 Min. 20 43 87 178 357 2 2 2 2 2 2 2 2 2 2 7 9.5 4.5 4.5 4.5 4.5 4.5 Typ. 23 46 92 183 366 Max. 26 49 97 188 375 Units ns
Data Sheet
Notes With SMPL_MODE = 0 (3/4-bit sampling) and zero offset. With respect to Min. Input Data Sampling Point
2
Local/Backplane Serial Input Set-up Time
ns
3
Local/Backplane Serial Input Hold Time
ns
With respect to Max. Input Data Sampling Point
4 5
Output Frame Boundary Offset Local/Backplane Serial Output Delay
ns ns CL=50pF These numbers are referencing output frame boundary.
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Zarlink Semiconductor Inc.
ZL50050
Data Sheet
FP8i C8i CK_int *
tIDS8 tSIS8 tSIH8
L/BSTi0-15 8.192 Mbps
1
0
7
6
5
4
3
2
1
tIDS4
tSIS4 tSIH4
L/BSTi0-15 4.096 Mbps
Bit0 Ch63
Bit7 Ch0
Bit6 Ch0
Bit5 Ch0
Bit4 Ch0
tIDS2
tSIS2 tSIH2
Bit7 Ch0 Bit6 Ch0
L/BSTi0-15 2.048 Mbps
Bit0 Ch31
tOFBOS FP8o C8o CK_int *
tSOD8
L/BSTo0-15 8.192 Mbps
Bit1 Ch127
Bit0 Ch127
Bit7 Ch0
Bit6 Ch0
Bit5 Ch0
Bit4 Ch0
Bit3 Ch0
Bit2 Ch0
Bit1 Ch0
tSOD4
L/BSTo0-15 4.096 Mbps
Bit0 Ch63
Bit7 Ch0
Bit6 Ch0
Bit5 Ch0
Bit4 Ch0
tSOD2
L/BSTo0-15 2.048 Mbps
Bit0 Ch31
Bit7 Ch0
Bit6 Ch0
Note * : CK_int is the internal clock signal of 131.072 MHz
Figure 26 - ST-BUS Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps)
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Zarlink Semiconductor Inc.
ZL50050
Data Sheet
FP8i C8i CK_int * tIDS32 tSIS32 tSIH32 L/BSTi0-7 32.768 Mbps
2 1 0 7 6 5 4 3 2
tIDS16
tSIS16 tSIH16
L/BSTi0-15 16.384 Mbps
Bit1 Ch255
Bit0 Ch255
Bit7 Ch0
Bit6 Ch0
Bit5 Ch0
tOFBOS FP8o C8o CK_int * tSOD32 L/BSTo0-7 32.768 Mbps
Bit1 Ch511 Bit1 Ch511 Bit0 Ch511 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0 Bit3 Ch0 Bit2 Ch0
tSOD16 L/BSTo0-15 16.384 Mbps
Bit0 Ch255 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0
Note *: CK_int is the internal clock signal of 131.072 MHz
Figure 27 - ST-BUS Local/Backplane Data Timing Diagram (32 Mbps, 16 Mbps)
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Zarlink Semiconductor Inc.
ZL50050
Data Sheet
FP8i C8i CK_int *
tIDS8 tSIS8 tSIH8
L/BSTi0-15 8.192 Mbps
6 7 0 1 2 3 4 5 6
tIDS4
tSIS4 tSIH4
L/BSTi0-15 4.096 Mbps
Bit7 Ch63
Bit0 Ch0
Bit1 Ch0
Bit2 Ch0
Bit3 Ch0
tIDS2
tSIS2 tSIH2
Bit0 Ch0 Bit1 Ch0
L/BSTi0-15 2.048 Mbps
Bit7 Ch31
tOFBOS
FP8o C8o CK_int *
tSOD8
L/BSTo0-15 8.192 Mbps
Bit6 Ch127 Bit7 Ch127 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0 Bit4 Ch0 Bit5 Ch0 Bit6 Ch0
tSOD4
L/BSTo0-15 4.096 Mbps
Bit7 Ch63 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0
tSOD2
L/BSTo0-15 2.048 Mbps
Bit7 Ch31 Bit0 Ch0 Bit1 Ch0
Note *: CK_int is the internal clock signal of 131.072 MHz
Figure 28 - GCI-Bus Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps)
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Zarlink Semiconductor Inc.
ZL50050
Data Sheet
FP8i C8i CK_int * tIDS32 tSIS32 tSIH32 L/BSTi0-7 32.768 Mbps
2 1 0 7 6 5 4 3 2
tIDS16
tSIS16 tSIH16
L/BSTi0-15 16.384 Mbps
Bit6 Ch255
Bit7 Ch255
Bit0 Ch0
Bit1 Ch0
Bit2 Ch0
tOFBOS FP8o C8o CK_int * tSOD32 L/BSTo0-7 32.768 Mbps
Bit5 Ch511 Bit6 Ch511 Bit7 Ch511 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0 Bit4 Ch0 Bit5 Ch0
tSOD16 L/BSTo0-15 16.384 Mbps
Bit7 Ch255 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0
Note *: CK_int is the internal clock signal of 131.072 MHz
Figure 29 - GCI-Bus Local/Backplane Data Timing Diagram (32 Mbps, 16 Mbps)
88
Zarlink Semiconductor Inc.
ZL50050
Local and Backplane Output High-Impedance Timing Characteristic 1 2 STo delay - Active to High-Z - High-Z to Active Output Driver Enable (ODE) Delay to Active Data Output Driver Enable (ODE) Delay to High-Impedance Sym. tDZ tZD tODE tODZ Min. Typ. 4 4 Max. 6 6 14 14 Unit s ns ns ns ns
Data Sheet
Test Conditions RL=1k, CL=50pF, See Note 1
RL=1k, CL=50pF, See Note 1 RL=1k, CL=50pF, See Note 1
Note 1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
CLK tDZ STo Valid Data tZD STo HiZ
VTT
HiZ
VTT
Valid Data
VTT
Figure 30 - Serial Output and External Control
ODE tODE STo Hi-Z tODZ
VTT
Valid Data
Hi-Z
VTT
Figure 31 - Output Driver Enable (ODE)
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Zarlink Semiconductor Inc.
ZL50050
Input Clock Jitter Tolerance Jitter Frequency 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 kHz 10 kHz 50 kHz 66 kHz 83 kHz 95 kHz 100 kHz 200 kHz 300 kHz 400 kHz 500 kHz 1 MHz 2 MHz 4 MHz 16.384 Mbps Data Rate Jitter Tolerance 1200 1200 150 110 80 70 25 17 17 17 17 17 17 17 32.768 Mbps Data Rate Jitter Tolerance 600 600 80 50 35 30 20 14 14 14 14 14 14 14
Data Sheet
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Zarlink Semiconductor Inc.
ZL50050
Non-Multiplexed Microprocessor Port Timing Characteristics 1 2 3 4 5 6 7 CS setup from DS falling R/W setup from DS falling Address setup from DS falling CS hold after DS rising R/W hold after DS rising Address hold after DS rising Data setup from DTA Low on Read Sym. tCSS tRWS tADS tCSH tRWH tADH tRDS Min. 0 9 9 0 9 9 5 12 4.5 9 9 88 80 tAKH 11 Typ. Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions
Memory Read Register Read CL=60pF CL=60pF, RL=1k Note 1
8 9 10 11
Data hold on read Data setup on write Data hold on write Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory Acknowledgment Hold Time
tRDH tWDS tWDH tAKD
CL=60pF CL=60pF CL=60pF, RL=1k, Note 1
12
Note: High Impedance is measured by pulling to the appropriate rail with RL , with timing corrected to cancel time taken to discharge CL. Note: There must be a minimum of 30 ns between CPU accesses, to allow the device to recognize the accesses as separate (i.e., a minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion of CS and/or DS to initiate the next access).
DS
tCSS
tCSH
VTT VTT
CS tRWS R/W tADS A0-A14
VALID ADDRESS
tRWH VTT tADH VTT tRDH
D0-D15 READ tWDS D0-D15 WRITE
VALID READ DATA
VTT tWDH
VALID WRITE DATA
VTT
tRDS
DTA
tAKD
VTT tAKH
Figure 32 - Motorola Non-Multiplexed Bus Timing
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Zarlink Semiconductor Inc.
ZL50050
AC Electrical Characteristics - JTAG Test Port Timing Characteristic 1 2 3 4 5 6 7 8 9 TCK Clock Period TCK Clock Pulse Width High TCK Clock Pulse Width Low TMS Set-up Time TMS Hold Time TDi Input Set-up Time TDi Input Hold Time TDo Output Delay TRST pulse width Sym. tTCKP tTCKH tTCKL tTMSS tTMSH tTDIS tTDIH tTDOD tTRSTW 200 Min. 100 80 80 10 10 20 60 30 Typ. Max. Units ns ns ns ns ns ns ns ns ns
Data Sheet
Notes
CL=30pF
Characteristics are over recommended operating conditions unless otherwise stated.
tTCKL TCK
tTCKH
tTCKP
tTMSS TMS
tTMSH
tTDIS tTDIH TDi tTDOD TDo
tTRSTW TRST
Figure 33 - JTAG Test Port Timing Diagram
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Zarlink Semiconductor Inc.
J
TOP VIEW
DIMENSION MIN MAX A 1.35 (1.55) 1.75 (1.97) A1 0.30 0.50 A2 0.75 0.85 D 15.00 BSC 13.70 D1 12.95 E 15.00 BSC E1 13.70 12.95 1.0 REF. I J 1.0 REF. 0.40 0.60 b 1.00 BSC e N 196 2 LAYERS (4 LAYERS)
I
BOTTOM VIEW
Conforms to JEDEC MS - 034 Except dimensions 'A1' and 'b'.
NOTES:1. Controlling dimensions are in MM. 2. Seating plane is defined by the spherical crown of the solder balls. 3. Not to scale. 4. Ball arrangement: 14 x 14 array
SIDE VIEW
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes:
ISSUE ACN DATE APPRD.
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